SP5848 datasheet(4/9 Pages) MITEL

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SP5848

Preliminary Information

Absolute maximum Ratings

All voltages referred to Vee at 0V

Characteristic

Value

Conditions

Min

Max

Units

Supply voltages

-0.3

RF1 input voltage

2.5

Vp-p

Differential

RF2 input voltage

2.5

Vp-p

Differential

All I/O ports DC offset

-0.3

Vcc+0.3

Storage temperature

-55

+125

°C

Junction temperature

150

°C

Package thermal resistance

chip to ambient

100

°C/W

chip to case

°C/W

Power consumption with all

121

All ports off

Vcc =5.5V

ESD protection

Mil std 883 latest revision methood 3015

class 1

Functional Description

The SP5848 contains two PLL frequency synthesiser

loops, each independently programmable from a 3-wire

bus. The device is optimised for application in double

conversion tuners where synthesiser 1 would form part

of the upconverter and synthesiser 2 part of the down

converter. Both loops are optimised for application in low

phase noise loops and furtherly synthesiser 2 offers low

comparison frequencies. A block diagram is contained in

Figure 1.

The device is programmed via a 3-wire bus where data

is fed on serial data and clock lines and is gated by an

enable line. Figure 3 indicates the format of the data.

The sequence and timing of data load is described below

in ‘programming mode’ description. Each synthesiser is

independently addressable and is defined by the LSB bit

within the data transmission.

A common reference frequency source and reference

divider is used to derive the comparison frequency for

both PLL loops. The reference division ratio is

programmable via the data bus as defined in Tables1

and 2.

The charge pump current for each loop is also

programmable via the data bus as defined in Tables 3

and 4

Two switching ports are provided to control switching

functions within the tuner. These ports also access test

signals within the PLL as defined in Figure 7. Ports

power up in high impedance state.

Programming Mode

The SP5848 is designed to be programmed from a

standard 3-wire bus consisting of clock, data and enable,

where the serial clock and data lines can be shared with

other devices and the enable line is a unique line for

individual device selection. To simplify programming

each synthesiser is independently addressed, with the

required loop being selected by the LSB bit , which

functions as the address, therefore to fully program the

device two complete data transmissions must be sent.

The data format for each transmission is contained in

Figure 3.

Test modes as described in Figure 7, can be invoked by

setting bit T0 in synthesiser 2 data word to a ‘1’ and

sending control data for bits T1-T2. In normal operation

where T0 is set to a ‘0’ bits T1 and T2 do not need to be

transmitted

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