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LM89 Datasheet(PDF) 7 Page - Texas Instruments |
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LM89 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 37 page ![]() VIH VIL SMBCLK P S VIH VI L SMBDAT tBUF tHD;STA tLOW tR tHD;DAT tHIGH tF tSU;DAT tSU;STA tSU;STO P LM89 www.ti.com SNIS128D – AUGUST 2002 – REVISED JUNE 2014 8.8 SMBus Digital Switching Characteristics Unless otherwise noted, these specifications apply for VDD = +3.0Vdc to +3.6Vdc, CL (load capacitance) on output lines = 80 pF. Unless otherwise noted, MIN and MAX limits apply for TA = TJ = TMIN to TMAX and typical limits TA= TJ= +25°C. The switching characteristics of the LM89 fully meet or exceed the published specifications of the SMBus version 2.0. The following parameters are the timing relationships between SMBCLK and SMBData signals related to the LM89. They adhere to but are not necessarily the SMBus bus specifications. SYMBOL PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) Unit fSMB SMBus Clock Frequency 10 100 kHz tLOW SMBus Clock Low Time from VIN(0)max to VIN(0)max 4.7 25,000 µs tHIGH SMBus Clock High Time from VIN(1)min to VIN(1)min 4.0 µs tR,SMB SMBus Rise Time (3) 1 µs tF,SMB SMBus Fall Time (4) 0.3 µs tOF Output Fall Time CL = 400pF, 250 ns IO = 3mA, (4) tTIMEOUT SMBData and SMBCLK Time Low for Reset 25 35 ms of Serial Interface (5) tSU;DAT Data In Setup Time to SMBCLK High 250 ns tHD;DAT Data Out Stable after SMBCLK Low 300 900 ns tHD;STA Start Condition SMBData Low to SMBCLK 100 ns Low (Start condition hold before the first clock falling edge) tSU;STO Stop Condition SMBCLK High to SMBData 100 ns Low (Stop Condition Setup) tSU;STA SMBus Repeated Start-Condition Setup 0.6 µs Time, SMBCLK High to SMBData Low tBUF SMBus Free Time Between Stop and Start 1.3 µs Conditions (1) Limits are specific to TI's AOQL (Average Outgoing Quality Level). (2) Typical values are at TA = 25°C and represent most likely parametric norm. (3) The output rise time is measured from (VIN(0)max + 0.15V) to (VIN(1)min − 0.15V). (4) The output fall time is measured from (VIN(1)min - 0.15V) to (VIN(1)min + 0.15V). (5) Holding the SMBData and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the LM89's SMBus state machine, therefore setting SMBData and SMBCLK pins to a high impedance state. Figure 2. SMBus Communication Copyright © 2002–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM89 |
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