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Z8018233FSC Datasheet(PDF) 95 Page - Zilog, Inc.

Part # Z8018233FSC
Description  ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP??
PDF  109 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8018233FSC Datasheet(HTML) 95 Page - Zilog, Inc.

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3-95
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
PRELIMINARY
Zilog
DS971820600
Table C. Z85230 General Timing Table
20 MHz
No.
Symbol
Parameter
Min
Max
Notes
1
TdPC(REQ)
/PCLK to W/REQ Valid
70
2
TdPC(W)
/PCLK to Wait Inactive
170
3
TsRxC(PC)
/RxC to /PCLK Setup Time
N/A
[1,4]
4
TsRxD(RxCr)
RxD to /RxC Setup Time
0
[1]
5
ThRxD(RxCr)
RxD to /RxC Hold Time
45
[1]
6
TsRxD(RxCf)
RxD to /RxC Setup Time
0
[1,5]
7
ThRxD(RxCf)
RxD to /RxC Hold Time
45
[1,5]
8
TsSY(RxC)
/SYNC to /RxC Setup Time
–90
[1]
9
ThSY(RXC)
/SYNC to/RxC Hold Time
5TcPc
[1]
10
TsTxC(PC)
/TxC to /PCLK Setup Time
N/A
[2,4]
11
TdTxCf(TXD)
/TxC to TxD Delay
70
[2]
12
TdTxCr(TXD)
/TxC to TxD Delay
70
[2,5]
13
TdTxD(TRX)
TxD to TRxC Delay
70
14
TwRTxh
RTxC High Width
70
[6]
15
TwRTxI
TRxC Low Width
70
[6]
16a
TcRTx
RTxC Cycle Time
200
[6,7]
16b
TxRx(DPLL)
DPLL Cycle Time Min
50
[7,8]
17
TcRTxx
Crystal Osc. Period
61
1000
[3]
18
TwTRxh
TRxC High Width
70
[6]
19
TwTRxl
TRxC Low Width
70
[6]
20
TcTRx
TRxC Cycle Time
200
[6,7]
21
TwExT
DCD or CTS Pulse Width
60
22
TwSY
SYNC Pulse Width
60
Notes:
These AC parameter values are preliminary and subject to change without notice.
[1]
RxC is /RTxC or /TRxC, whichever is supplying the receive clock.
[2]
TxC is /TRxC or /RTxC, whichever is supplying the transmit clock.
[3]
Both /RTxC and /SYNC have 30 pF capacitors to ground connected to them.
[4]
Synchronization of RxC to PCLK is eliminated in divide by four operation.
[5]
Parameter applies only to FM encoding/decoding.
[6]
Parameter applies only for transmitter and receiver; DPLL and baud
rate generator timing requirements are identical to case PCLK requirements.
[7]
The maximum receive or transmit data rate is 1/4 PCLK.
[8]
Applies to DPLL clock source only. Maximum data rate of 1/4 PCLK
still applies. DPLL clock should have a 50% duty cycle.



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