Z8018233FSC datasheet(69/109 Pages) ZILOG

69 / 109 page

3-69

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

16550 MIMIC REGISTERS

The Z80182/Z8L182 contains the following set of registers

for interfacing with the PC/XT/AT.

– Receive Buffer Register

– Transmit Holding Register

– Interrupt Enable Register

– Interrupt Identification Register

– FIFO Control Register

– Line Control Register

– Modem Control Register

– Line Status Register

– Modem Status Register

– Scratch Register

– Divisor Latch Least/Most Significant Bytes

– FIFO Control Register

These registers emulate the 16550 UART and enable the

PC/XT/AT to interface with them as with an actual 16550

UART. This allows the Z80182/Z8L182 to be software

compatible with existing modem software.

0000000

Receive Buffer Register

Figure 69. Receive Buffer Register

(PC Read Only, Address 00H, DLAB=0, R/W=Read)

(Z180™ MPU Write Only, Address XXF0H)

Receive Buffer Register

When the Z180 has assembled a byte of data to pass to the

PC/XT/AT, it places it in the Receive Buffer Register. If the

Received Data Available interrupt is enabled then an

interrupt is generated for the PC/XT/AT and the Data Ready

bit is set (if the Receive Timer is enabled, the interrupt and

setting of the Data Ready bit is delayed until after the timer

times out). Also the shadowed bits of the Line Status

Z180 MPU writes to the Receive Buffer Register (See Line

Status Register Bits 1, 2, 3 and 4). This allows a simultaneous

setting of error bits when the data is written to the Receive

Buffer Register. In FIFO, mode this address is used to read

(PC) and write (Z180) the Receive FIFO.

0000000

Transmitter Holding Register

Figure 70. Transmit Holding Register

(PC Write Only, Address 00H, DLAB=0, R/W=Write)

(Z180 MPU Read Only, Address xxF0H)

Transmit Holding Register

When the PC/XT/AT writes to the Transmit Holding Register,

the Z80182/Z8L182 responds by setting the appropriate

bit in the IP register and by generating an interrupt to the

Z180 MPU if it is enabled. When the Z180 MPU reads this

the transmitter timer is enabled , this bit is set after the timer

times out). In FIFO mode of operation, this address is used

to read (Z180) and write (PC) the Transmitter FIFO.

000000

DMA Mode Select

Reserved (Tx Overrun, MPU only)

Reserved (FCR Write, MPU only)

RCVR Trigger (LSB)

RCVR Trigger (MSB)

XMIT FIFO Reset

RCVR FIFO Reset

FIFO Enable

Figure 71. FIFO Control Register

(PC Write Only, Address 02H)

(Z180 MPU Read Only, Address xxE9H)

Z8018233FSC Datasheet(PDF) 69 Page - Zilog, Inc.

Z8018233FSC Datasheet(HTML) 69 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL