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Z8018233FSC Datasheet(PDF) 40 Page - Zilog, Inc. |
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Z8018233FSC Datasheet(HTML) 40 Page - Zilog, Inc. |
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40 / 109 page ![]() 3-40 Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL PRELIMINARY Zilog DS971820600 DMA REGISTERS (Continued) DE1 DE0 DIE0 - DIME 0 R/W 0 R/W 1 W 1 W 00 R/W 10 R R/W DMA Master Enable Addr 30H Bit Upon Reset DIE1 /DWE0 DMA Interrupt Enable 1, 0 DMA Enable Bit Write Enable 1, 0 DMA Enable Ch 1, 0 /DWE1 DSTAT R/W Figure 40. DMA Status Register - - SM0 MMOD - 11 0 R/W 0 R/W 00 R/W 01 R/W Memory MODE Select Addr 31H Bit Upon Reset SM1 DM0 Ch 0 Source Mode 1, 0 Ch 0 Destination Mode 1, 0 DM1 DMODE R/W R/W DM1, 0 00 01 10 11 Destination M M M I/O Address DAR0+1 DAR0-1 DAR0 Fixed DAR0 Fixed SM1, 0 00 01 10 11 Source M M M I/O Address SAR0+1 SAR0-1 SAR0 Fixed SAR0 Fixed 0 1 Mode Cycle Steal Mode Burst Mode MMOD Figure 41. DMA Mode Registers |
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