Z89176 datasheet(3/68 Pages) ZILOG

3 / 68 page

Z89175/Z89176

Zilog

Voice Processing Controllers

DS97TAD0100

P R E L I M I N A R Y

PIN DESCRIPTION

Figure 1. Z89175/176 Functional Block Diagram

Port 0

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

P24

P25

P26

P27

P31

P32

P33

P40

P41

P42

P43

P44

P45

P46

P47

P50

P51

P52

P53

P54

P55

P56

P57

RMLS

/AS

/DS

R/W

Timer 0

Capture Reg.

Port 3

Port 1

Port 4

Port 2

Port 5

Timer 1

256 x 8 Bit

24 Kbytes

Program

ROM

(Z89175)

Z8 Core

Internal Address Bus

Internal Data Bus

Expanded Register

File

(Z8)

Peripheral

(DSP)

Expanded

Extended Bus of the DSP

8K Words

Program

ROM

DSP Core

Internal Address Bus

Internal Data Bus

DSP Port

PWM

(10-Bit)

ADC

(8-Bit)

Timer 2

Timer 3

Extended Bus of the DSP

Ext.

Memory

Control

OSC

Power

XTAL1

XTAL2

VDD

GND

/RESET

INT 1

INT 2

DSP0

DSP1

AN IN

AN VDD

AN GND

VREF+

VREF-

PWM

256 Word

RAM 0

256 Word

RAM 1

P34

P35

P36

P37

Input

Output

I/O

(Bit

Programmable)

I/O

(Bit

Programmable)

Address

or I/O

(Nibble

Programmable)

Address/Data

or I/O

(Byte

Programmable)

I/O

(Bit

Programmable)

mailbox

OSC1

OSC2

32 kHz

OSC

Z89176 Datasheet(PDF) 3 Page - Zilog, Inc.

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