Z89176 datasheet(39/68 Pages) ZILOG

39 / 68 page

Z89175/Z89176

Zilog

Voice Processing Controllers

DS97TAD0100

P R E L I M I N A R Y

Port Configuration Register (PCON). The PCON regis-

ter configures the comparator output on Port 3. The PCON

File at Bank F, location 00H.

Comparator Output Port 3 (D0). Bit 0 controls the com-

parator use in Port 3. A 1 in this location brings the com-

parator outputs to P34 and P35, and a 0 releases the Port

to its standard I/O configuration.

Port 4 and 5 Configuration Register (P45CON). The

P45CON register configures Port 4 and Port 5, individual-

ly, to open-drain or push-pull active. This register is located

in the Expanded Register File at Bank F, location 06H (Fig-

ure 26).

Port 4 Open-Drain (D0). Port 4 can be configured as an

open-drain by resetting this bit (D0 = 0) or configured as

push-pull active by setting this bit (D0 = 1). The default val-

ue is 1.

Port 5 Open-Drain (D4). Port 5 can be configured as an

open-drain by resetting this bit (D4 = 0) or configured as

push-pull active by setting this bit (D4 = 1). The default val-

ue is 1.

Power-On Reset (POR). A timer circuit clocked by a ded-

icated on-board RC oscillator is used for the Power-On Re-

set (POR) timer function. The POR time allows VCC and

the oscillator circuit to stabilize before instruction execu-

tion begins.

The POR timer circuit is a one-shot timer triggered by one

of three conditions:

Power fail to Power OK status;

Stop-Mode Recovery (if D5 of SMR=1);

WDT time-out.

The POR time is a nominal 5 ms. Bit 5 of the STOP mode

ter Stop-Mode Recovery (typical for external clock, RC/LC

oscillators).

HALT. HALT turns off the internal CPU clock, but not the

XTAL oscillation. The counter/timers and external inter-

rupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The de-

vices are recovered by interrupts, either externally or inter-

nally generated.

STOP. This instruction turns off the internal clock and ex-

ternal crystal oscillation. It reduces the standby current to

µA or less. The STOP mode is terminated by a reset

only, either by WDT time-out, POR, SMR, or external re-

set. This causes the processor to restart the application

program at address 000CH. In order to enter STOP (or

HALT) mode, it is necessary to first flush the instruction

pipeline to avoid suspending execution in mid-instruction.

To do this, the user must execute a NOP (opcode=FFH)

immediately before the appropriate Sleep instruction, i.e.,

Figure 25. Port Conﬁguration Register (PCON)

D7 D6

D1 D0

PCON (F) %00

R Always "1"

W 0 P34,P37 Standard output

1 P34,P37 Comparator output

R Always "1"

W No effect

Note: Reset condition is 11111110

NOP

; clear the pipeline

STOP

; enter Stop mode

NOP

; clear the pipeline

HALT

; enter Halt mode

Z89176 Datasheet(PDF) 39 Page - Zilog, Inc.

Z89176 Datasheet(HTML) 39 Page - Zilog, Inc.

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