Z89176 datasheet(49/68 Pages) ZILOG

49 / 68 page

Z89175/Z89176

Zilog

Voice Processing Controllers

DS97TAD0100

P R E L I M I N A R Y

Figure 34. Interprocessor Interrupts Structure

After serving IRQ3,

set D0 to clear the

interrupt request.

The DSP sets D9 to

interrupt Z8 via Z8 IRQ3.

IRQ3 of the Z8

DSP INT2

After serving INT2,

set D4 to clear the

interrupt request.

On the Z8, set D1 to

interrupt DSP via DSP INT2.

DSP Side

Z8 Side

DSP CON

ICR

(EXT4)

Table 15. EXT4 DSP Interrupt Control Register (ICR) Deﬁnition

Field

Position

Attrib

Value

Label

DSP_IRQ2

f---------------

Set_IRQ2

Reset_IRQ2

f---------------

No effect

DSP_IRQ1

-e--------------

Set_IRQ1

Reset_IRQ1

-e--------------

No effect

DSP_IRQ0

--d-------------

Set_IRQ0

Reset_IRQ0

--d-------------

No effect

DSP_MaskINT2

---c------------

R/W

Enable_INT2

Disable_INT2

DSP_MaskINT1

----b-----------

R/W

Enable_INT1

Disable_INT1

DSP_MaskINT0

-----a----------

R/W

Enable_INT0

Disable_INT0

Z8_IRQ3

------9---------

Return "0"

------9---------

Set_Z8_IRQ3

Reset_Z8_IRQ3

DSPintEnable

-------8--------

R/W

Enable

Disable

DSP_IPR2

--------7-------

R/W

Binary

IPR2

DSP_IPR1

---------6------

R/W

Binary

IPR1

DSP_IPR0

----------5-----

R/W

Binary

IPR0

Clear_IRQ2

-----------4----

Return "0"

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