F1950Z datasheet(4/17 Pages) IDT

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7-bit 0.25 dB Digital Step Attenuator

150 MHz to 4000 MHz

Glitch-Free

TM Digital Step Attenuator

Rev1 March 2012

IDTF1950

DATASHEET

SERIAL CONTROL MODE

Serial mode is selected by floating VMODE (pin3) or pulling it to a voltage > VIH. In serial mode data is clocked in LSB

first. Note the timing diagram below.

Note – The IDTF1950 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device

is not being programmed. When Latch enable is high (> VIH), the CLK input is disabled and DATA will not be clocked

into the shift register. It is recommended that LE be pulled high (> VIH) when the device is not being programmed.

SERIAL REGISTER TIMING DIAGRAM: (Note the Timing Spec Intervals in Blue)

SERIAL MODE DEFAULT CONDITION:

When the device is powered up it will default to the Maximum Attenuation setting as described below:

Note that for the F1950 in all cases (High or 1) = Attenuation Stepped IN. (0 or Low) = Attenuation Stepped OUT.

SERIAL MODE TIMING TABLE:

Interval

Symbol

Description

Min

Spec

Max

Spec

Units

Parallel to Serial Setup Time

100

nsec

Serial Data Hold Time

nsec

LE delay from final serial clock rising edge

nsec

Data Word 8 bits

0.5 dB

CLK

DATA

Data Word

Latched into

Active Register

LSB

0.25 dB

1 dB

2 dB

4 dB

8 dB

16 dB

MSB

RSV

VMODE

Spec

Interval

Time

Default Register Settings

RSV

MSB

LSB

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