INA206

x20

12V Supply

12V Load

Shutdown

Warning

3.3V Supply

V

S

OUT

CMP1 IN+

CMP2 IN–

CMP2 IN+/0.6 REF

GND

V

IN+

V

IN–

1.2V REF OUT

CMP1 OUT

CMP2 OUT

CMP2 DELAY

2.5V Reference

1.2V REF

CMP1 IN–/0.6 REF

R

3m

SHUNT

W

C

0.1 F

(0.5s)

DELAY

µ

D

DELAY

t

C

(in F)

5

m

=

0V

0.6V

V

IN

CMP Out

RESET

U2

U1

0.6V

1.2V

I2

120nA

I1

120nA

C

DELAY

INA206, INA207, INA208

SBOS360F – JUNE 2006 – REVISED NOVEMBER 2015

www.ti.com

Feature Description (continued)

Figure 30. Simplified Model of the Comparator 2 Delay Circuit

Figure 31. Comparator 1 Latching Capability

8.3.4 Comparator Delay (14-Pin Version Only)

The Comparator 2 programmable delay is controlled by a capacitor connected to the CMP2 Delay Pin; see

Figure 40. The capacitor value (in µF) is selected by using Equation 1.

(1)

A simplified version of the delay circuit for Comparator 2 is shown in Figure 30. The delay comparator consists of

two comparator stages with the delay between them. Note that I1 and I2 cannot be turned on simultaneously; I1

corresponds to a U1 low output and I2 corresponds to a U1 high output. Using an initial assumption that the U1

begins to ramp toward a 0.6-V threshold. When the voltage crosses this threshold, the U2 output goes high while

the voltage at U2 +IN continues to ramp up to a maximum of 1.2 V when given sufficient time (twice the value of

returning to low exhibits the same delay.

Figure 32. Server 12-V Supply Current Monitor

16

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