DIX4192IPFB datasheet(22/69 Pages) TI1

22 / 69 page

VIO

10kW

Tothe

outputsf

INT

additionalDIX4192 devices

Interrupt

Logic

DIX4192

MCU,DSP,

orLogic

INT 23

Interrupt

Input

DIX4192

SBFS031D – JANUARY 2006 – REVISED JANUARY 2016

www.ti.com

Feature Description (continued)

9.3.7 General-Purpose Digital Outputs

The DIX4192 includes four general-purpose digital outputs, GPO1 through GPO4 (pins 26 through 29,

respectively). A GPO pin may be programmed to a static high or low state. Alternatively, a GPO pin may be

connected to one of 13 internal logic nodes, allowing the GPO pin to inherit the function of the selected signal.

Control registers 0x1B through 0x1E are used to select the function of the GPO pins. For details regarding GPO

output configuration, refer to Control Registers. Table 1 summarizes the available output options for the GPO

pins.

Table 1. General-Purpose Output Pin Configurations

GPOn3

GPOn2

GPOn1

GPOn0

GPOn FUNCTION

GPOn is forced low (default)

GPOn is forced high

Reserved

DIT interrupt flag; active low

DIR interrupt flag; active low

DIR 50/15-

μs emphasis flag; active low

DIR non-audio data flag; active high

DIR non-valid data flag; active high

DIR channel status data serial output

DIR user data serial output

DIR block start clock output

DIR COPY bit output

(0 = copyright asserted, 1 = copyright not asserted)

DIR L (or origination) bit output

(0 = 1st generation or higher, 1 = original)

DIR Parity error flag; active high

DIR internal sync clock output; may be used as the data clock for the channel

status and user data serial outputs.

DIT internal sync clock

9.3.8 Interrupt Output

The DIX4192 includes multiple internal status bits, many of which may be set to trigger an interrupt signal. The

interrupt signal is output at INT (pin 23), which is an active low, open-drain output. The INT pin requires a pullup

resistor to the VIO supply rail. The value of the pullup is not critical, but a 10-k

Ω device must be sufficient for

most applications. Figure 18 shows the interrupt output pin connection. The open-drain output allows interrupt

pins from multiple DIX4192 devices to be connected in a wired OR configuration.

Figure 18. Interrupt Output Pin Connections

Submit Documentation Feedback

Product Folder Links: DIX4192

DIX4192IPFB Datasheet(PDF) 22 Page - Texas Instruments

DIX4192IPFB Datasheet(HTML) 22 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

Datasheet Download

Link URL