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DIX4192IPFB Datasheet(PDF) 7 Page - Texas Instruments |
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DIX4192IPFB Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 69 page  DIX4192 www.ti.com SBFS031D – JANUARY 2006 – REVISED JANUARY 2016 Electrical Characteristics (continued) All specifications are at TA = 25°C, VDD18 = 1.8 V, VDD33 = 3.3 V, VIO = 3.3 V, and VCC = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Recovered clock output (RXCKO) intrinsic ps RMS Measured cycle-to-cycle 250 jitter DIGITAL AUDIO INTERFACE TRANSMITTER (DIT) Intrinsic output jitter Measured cycle-to-cycle 200 ps RMS AUDIO SERIAL PORTS (PORT A AND PORT B) fLRCK LRCK clock frequency 0 216 kHz tLRCKD LRCK clock duty cycle 50% fBCK BCK clock frequency 0 13.824 MHz tBCKH BCK high pulse width 10 ns tBCKL BCK low pulse width 10 ns tAIS Audio data Input (SDIN) set-up time 10 ns tAISH Audio data input (SDIN) hold time 10 ns tADD Audio data output (SDOUT) delay 10 ns HOST INTERFACE: SPI MODE fCCLK Serial clock (CCLK) frequency 0 40 MHz tCSCR CS falling to CCLK rising 8 ns tCFCS CCLK falling to CS rising 7 ns tCDS CDIN data set-up time 7 ns tCDH CDIN data hold time 6 ns tCFDO CCLK falling to CDOUT data valid 3 ns tCSZ CS rising to CDOUT high-impedance, 3 ns HOST INTERFACE: I2C STANDARD MODE(1) fSCL SCL clock frequency 0 100 kHz tHDSTA Hold time repeated START condition 4 μs tLOW Low period of SCL clock 4.7 μs tHIGH High period of SCL clock 4 μs tSUSTA Set-up time repeated START condition 4.7 μs tHDDAT Data hold time 0(2) 3.45(3) μs tSUDAT Data set-up time 250 ns tR Rise time for both SDA and SDL 1000 ns tF Fall time for both SDA and SDL 300 ns tSUSTO Set-up time for STOP condition 4 μs tBUF Bus free time between START and STOP 4.7 μs CB Capacitive load for each bus line 400 pF Noise margin at low level (including 0.1 × VIO V VNL hysteresis) Noise margin at high level (including 0.2 × VIO V VNH hysteresis) HOST INTERFACE: I2C FAST MODE(1) fSCL SCL clock frequency 0 400 kHz tHDSTA Hold time repeated START condition 0.6 μs tLOW Low period of SCL clock 1.3 μs tHIGH High period of SCL clock 0.6 μs tSUSTA Set-up time repeated START condition 0.6 μs tHDDAT Data hold time 0(2) 0.9(3) μs (1) All values referred to the VIH minimum and VIL maximum levels listed in the Digital I/O Characteristics section of this table. (2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum input level) to bridge the undefined region of the falling edge of SCL. (3) The maximum tHDDAT has only to be met if the device does not stretch the Low period (tLOW) of the SCL signal. Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DIX4192 |
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