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[v1-04] 2015-Jun-19

AS1382 − Application Information

The Resistor values for the circuit shown above can be

calculated with the following equation:

The output voltage can be adjusted by selecting different

values for R1 and R2. For R2 a value between 10k

Ω and 50kΩ is

recommended. To minimize current to FB pin it is

recommended to keep sum of R1 and R2 below 100 kΩ. It is also

recommended to keep VIN 500mV higher than VOUT.

An optional feedback capacitor (CFB) can be added in parallel

with R1 to reduce output ripple. Typical value for the CFB is

below 300pF

PCB Layout

Long printed circuit tracks can generate additional ripple and

noise that mask correct operation and prove difficult to

“de-bug” during production testing. Thus the input loop formed

by CIN, VIN and GND pins should be minimized. Similarly, the

output loop formed by COUT, VOUT and GND should also be

minimized. Figure 16 shows a PCB layout example for the

AS1382.

Figure 16:

PCB Layout Example For The Adjustable Variant

(EQ1)

VOUT

0.58V

------

Vin

GND

1 uH

2.5mm x 2.0mm

Mode

Vout

Cout

10 uF

1.6mm x 0.8mm

Cin

4.7 uF

1.6mm x

0.8mm

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