TAS5756M datasheet(33/104 Pages) TI1

33 / 104 page

SPK_OUTB+

SPK_OUTB-

SPK_OUTA+

SPK_OUTA-

SCLK

SDIN

MCLK

LRCK/FS

SPK_GAIN/FREQ

Internal Gate

Drive Regulator

GPIO1

GPIO0

GPIO2

ADR1

Analog

PWM

Modulator

Gate

Drives

Full Bridge

Power

Stage A

Output

Current

Monitoring

and

Protection

Full Bridge

Power

Stage B

Gate

Drives

Closed Loop Class D Amplifier

1.8-V

Regulator

Internal Voltage

Supplies

Charge

Pump

Serial

Audio

Port

Mini-DSP

Hybrid RAM/

ROM

Architecture

with

Several

Selectable

HybridFlows

DAC

Internal Control Registers and State Machines

Clock Monitoring

and Error Protection

Die Temperature

Monitoring and Protection

ADR0

SDA

SCL

SPK_FAULT

SPK_SD

Error Reporting

SDOUT

Internal

Voltage

Supplies

SPK_MUTE

TAS5756M

www.ti.com

SLAS988B – JUNE 2014 – REVISED AUGUST 2015

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Power-on-Reset (POR) Function

The TAS5756M device has a power-on reset function. This feature resets all of the registers to their default

configuration as the device is powering up. When the low-voltage power supply used to power DVDD, AVDD,

and CPVDD exceeds the POR threshold, the device holds sets all of the internal registers to their default values

and holds them there until it receives valid MCLK, SCLK, and LRCK/FS toggling for a period of approximately 4

ms. After the toggling period has passed, the internal reset of the registers is removed and the registers can be

programmed via the I2C Control Port.

8.3.2 Device Clocking

The TAS5756M devices have flexible systems for clocking. Internally, the device requires a number of clocks,

mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio

Interface in one form or another.

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