TAS5760MDAPR datasheet(39/84 Pages) TI1

39 / 84 page

TAS5760M

www.ti.com

SLOS772D – JULY 2013 – REVISED JULY 2015

NOTE

A higher gain setting can be used, provided the noise performance is acceptable and the

power delivered to the speaker remains within the safe operating area (SOA) of the

speaker, using the soft clipper if necessary to set the clip point within the SOA of the

speaker.

4. Characterize the clipping behavior of the system at the rated power.

–

If the system does not produce the target power before clipping that is required, increase the analog gain.

–

If the system meets the power requirements, but clipping is preferred at the rated power, use the soft

clipper or the digital clipper to set the clip point

–

If the system makes more power than is required but the noise performance is too high, consider

reducing the analog gain.

5. Repeat Step 4 until the optimum balance of power, noise, and clipping behavior is achieved.

9.4.2.5 I²C Software Control Port

The TAS5760M includes an I²C control port for increased flexibility and extended feature set.

9.4.2.5.1

Setting the I²C Device Address

Each device on the I²C bus has a unique address that allows it to appropriately transmit and receive data to and

from the I²C master controller. As part of the I²C protocol, the I²C master broadcast an 8-bit word on the bus that

contains a 7-bit device address in the upper 7 bits and a read or write bit for the LSB. The TAS5760M has a

configurable I²C address. The SPK_SLEEP/ADR can be used to set the device address of the TAS5760M. In

Software Control mode, the seven bit I²C device address is configured as “110110x[R/W]”, where “x” corresponds

to the state of the SPK_SLEEP/ADR pin at first power up sequence of the device. Upon application of the power

supplies, the device latches in the value of the SPK_SLEEP/ADR pin for use in determining the I²C address of

the device. If the SPK_SLEEP/ADR pin is tied LOW at power up (that is connected to the system ground), the

device address will be set to 1101100[R/W]. If it is pulled HIGH (that is connected to the DVDD supply), the

address will be set to 1101101[R/W] at power up.

9.4.2.5.2

General Operation of the I²C Control Port

The TAS5760M device has a bidirectional I²C interface that is compatible with the Inter IC (I²C) bus protocol and

supports both 100-kHz and 400-kHz data transfer rates. This is a slave-only device that does not support a

multimaster bus environment or wait-state insertion. The control interface is used to program the registers of the

device and to read device status.

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a

system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte

(8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is

acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master

device driving a START condition on the bus and ends with the master device driving a stop condition on the

bus. The bus uses transitions on the data pin (SDA) while the clock is HIGH to indicate START and STOP

conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal

data-bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 48.

The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another

device and then waits for an acknowledge condition. The TAS5760M holds SDA LOW during the acknowledge

clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the

sequence. All compatible devices share the same signals via a bidirectional bus using a wired-AND connection.

An external pullup resistor must be used for the SDA and SCL signals to set the HIGH level for the bus.

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