AP3595

Document number: DS36749 Rev. 1 - 2

18 of 23

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January 2014

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AP3595

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The conduction losses are the largest component of power dissipation for both the high-side and the low-side MOSFETs. These losses are

distributed between the two MOSFETs according to duty factor (see the equations below). Only the high-side MOSFET has switching losses since

the low-side MOSFETs body diode or an external Schottky rectifier across the lower MOSFET clamps the switching node before the synchronous

rectifier turns on. These equations assume linear voltage current transitions and do not adequately model power loss due to the reverse-recovery

of the low-side MOSFET body diode. The gate-charge losses are dissipated by

AP3595 and don’t heat the MOSFETs. However, large gate-

maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance

specifications. A separate heat sink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.

For the high-side and low-side MOSFETs, the losses are approximately given by the following equations:

duty cycle.

18. Layout Consideration

In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator.

With power devices switching at higher frequency, the resulting current transient will cause voltage spike across the interconnecting impedance

and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is

carrying the full load current. During turn-off, current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic

diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed

circuit traces should minimize interconnecting impedances and the magnitude of voltage spike.

Besides, signal and power grounds are to be kept separating and finally combined using ground plane construction or single point grounding. The

best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each channel, where there is less

noise. Noisy traces beneath the IC are not recommended. Figure 11 illustrates the layout, with bold lines indicating high current paths; these

traces must be short and wide. Components along the bold lines should be placed close together. Below is a checklist for your layout:

1. Keep the switching nodes (HGx, LGx, BOOTx, and PHASEx) away from sensitive small signal nodes since these nodes are fast moving signals.

Therefore keep traces to these nodes as short as possible and there should be no other weak signal traces in parallel with theses traces on any

layer.

2. The signals going through theses traces have both high dv/dt and high dI/dt with high peak charging and discharging current. The traces from

the gate drivers to the MOSFETs (HGx and LGx) should be short and wide.

3. Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide

layout plane between the two pads reduces the voltage bounce of the node. In addition, the large layout plane between the drain of the MOSFETs

4. For experiment result of accurate current sensing, the current sensing components are suggested to place close to the inductor part. To avoid

the noise interference, the current sensing trace should be away from the noisy switching nodes.

5. Decoupling capacitors, the resistor-divider, and the boot capacitor should be close to their pins. (For example, place the decoupling ceramic

capacitor as close as possible to the drain of the high-side MOSFET).The input bulk capacitors should be close to the drain of the high-side

MOSFET, and the output bulk capacitors should be close to the loads.

6. The input c

apacitor’s ground should be close to the grounds of the output capacitors and the low-side MOSFET.