LMK03328 datasheet(39/153 Pages) TI1

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LMK03328

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SNAS668A – AUGUST 2015 – REVISED JANUARY 2016

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If reducing frequency error of the crystal is of utmost improtance, a crystal with low pullability should be used. If

frequency margining or frequency spiking is desired, a crystal with high pullability should be used to ensure that

the desired frequency offset is added to the nominal oscillation frequency. A total of ±50 ppm pulling range is

obtained with a crystal whose ratio of shunt capacitance to motional capacitance (C0/C1) is no more than 250.

The programmable capacitors on LMK03328 can be tuned from 14 pF to 24 pF in steps of 14 fF using either an

analog voltage on GPIO5 in soft pin mode or via I2C in soft pin or hard pin mode. When using crystals with low

pullability, preferred method is to program R86.3 = 1, R86.2 = 0, and program the appropriate binary code to

R104 and R105, in this exact order, that sets the required on-chip load capacitance for least frequency error.

GPIO4 pin should be tied to VDD and GPIO5 pin should be floating when device is operating in soft pin mode.

Table 4 shows the binary code for on-chip load capacitance on each leg of crystal.

When using crystals with high pullability, same method as above can be repeated for setting a fixed frequency

offset to the nominal oscillation frequency according to Equation 4. In case of a closed loop system where the

crystal frequency can be dynamically changed based on a control signal, the LMK03328 should operate in soft

pin mode and R86.3 should be programmed to 0 and R86.2 should be programmed to 1. The GPIO5 pin is now

configured as an 8-level input with a full scale range of 0 V to 1.8 V and every 200 mV corresponds to a

frequency change, according to Equation 4. There are three possibilities to enable margining feature with GPIO5:

•

Programming R86.3 = 0 and R86.2 = 1. In this case, status of GPIO4 pin is ignored.

•

When R86.3 = 0 and R86.2 = 0 is programmed, GPIO4 should be tied to GND. Tying GPIO4 to VDD disables

GPIO5 for margining purposes and R94 and R95 determine the on-chip load capacitance for the crystal. If

any frequency offset is desired at the output, the appropriate binary code should be programmed to R94 and

R95.

•

When R86.3 = 1 and R86.2 = 0 is programmed, GPIO4 should be tied to GND. Tying GPIO4 to VDD disables

GPIO5 for margining purposes and R104 and R105 determine the on-chip load capacitance for the crystal. If

any frequency offset is desired at the output, the appropriate binary code should be programmed to R104 and

R105.

There are two possibilities to drive the GPIO5 pin:

•

The first method is to achieve the desired voltage between 0V to 1.8V according to Analog Input

Characteristics (GPIO[5]). The pulldown resistor value sets the voltage on GPIO[5] pin that falls within one of

eight settings whose pre-programmed on-chip crystal load capacitances are set by R88, R89, R90, R91, R92,

R93, R94, R95, R96, R97, R98, R99, R100, R101, R102 and R103.

•

The second method is using a low-pass filtered PWM signal to drive the 8-level GPIO5 pin as shown in

Figure 57. The PWM signal could be generated from the frequency difference between a highly stable TCXO

and the output of LMK03328 that is provided as a feedback into the GPIO5 pin and used to adjust the on-chip

load capacitance on the crystal input in order to reduce frequency errors from the crystal. This is a quick

alternative that produces a frequency error at the LMK03328's output and could be acceptable to any

application when compared to a full-characterization with a chosen crystal to understand the exact load

pulling required to minimize frequency error at the LMK03328's output. More details on frequency margining

are provided in the “Application Information” section.

LMK03328 Datasheet(PDF) 39 Page - Texas Instruments

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