LMK03328 datasheet(13/153 Pages) TI1

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LMK03328

www.ti.com

SNAS668A – AUGUST 2015 – REVISED JANUARY 2016

Product Folder Links: LMK03328

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(1)

Refer to Parameter Measurement Information for relevant test conditions.

(2)

An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.

(3)

Ensured by characterization.

8.17 AC-CML Output Characteristics

(1)

VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG = 3.3 V ± 5%, VDDO_x = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = -40°C to

85°C, output pair AC-coupled to 100

Ω differential load

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fOUT

Output Frequency(2)

1000

MHz

VOD

Output Voltage Swing

400

600

1000

VSS

Differential Output Peak-to-

Peak Swing

2 x

|VOD|

VOS

Output Common Mode

150

550

tSKEW

(3)

Output-to-output skew

CML-to-CML; same divide value

tPROP-DIFF

IN-to-OUT Propagation Delay

PLL Bypass

400

tR/tF

(3)

Output Rise/Fall Time

20% to 80%, < 300 MHz

190

300

±100 mV around center point, > 300 MHz

200

PN-Floor

Output Phase Noise Floor

(fOFFSET > 10 MHz)

156.25 MHz

-160

dBc/Hz

ODC(3)

Output Duty Cycle

45%

55%

(1)

Refer to Parameter Measurement Information for relevant test conditions.

(2)

Measured from -150 mV to +150 mV on the differential waveform (OUT minus nOUT) with the 300 mVpp measurement window

centered on the differential zero crossing.

(3)

Ensured by design.

(4)

Ensured by characterization.

8.18 HCSL Output Characteristics

(1)

VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG = 3.3 V ± 5%, VDDO_x = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = -40°C to

85°C, outputs with 50 ohms || 2 pF to GND.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fOUT

Output Frequency

400

MHz

VOH

Output High Voltage(2)

660

850

VOL

Output Low Voltage(2)

-150

150

VCROSS

Absolute Crossing Voltage(3)

250

550

VCROSS-

DELTA

Variation of VCROSS

(3)

140

tSKEW

(4)

Output-to-output skew

same divide value

100

tPROP-DIFF

IN-to-OUT Propagation Delay

PLL Bypass

400

dV/dt(4)

Slew Rate(2)

2.25

V/ns

PN-Floor

Output Phase Noise Floor

(fOFFSET > 10 MHz)

100 MHz

-158

dBc/Hz

ODC(4)

Output Duty Cycle

45%

55%

8.19 Power-On/Reset Characteristics

VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG = 3.3 V ± 5%, VDDO_x = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = -40°C to

85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VTHRESH

Threshold Voltage

2.72

2.95

VDROOP

Allowable Voltage Droop

0.1

tSTART-XTAL Startup Time with 25 MHz

XTAL

Measured from time of supply reaching 3.135 V to

time of output frequency accurate to ±300 ppm

tSTART-CLK

Startup Time with 25 MHz

Clock Input

Measured from time of supply reaching 3.135 V to

time of output frequency accurate to ±300 ppm

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