Rev 2.0, May 12, 2008

Page 8 of 14

SL23EP09

AC Electrical Specifications (VDD=3.3V and 2.5V)

Notes:

1. For the given maximum loading conditions. See CL in Operating Conditions Table.

2. Parameter is guaranteed by design and characterization. Not 100% tested in production.

Symbol

Description

Condition

Min

Typ

Max

Unit

FMAX

Maximum Frequency

(Input=Output )

[1]

3.3V High Drive

10

–

220

MHz

3.3V Standard Drive

10

–

200

MHz

2.5V High Drive

10

–

180

MHz

2.5V Standard Drive

10

–

167

MHz

INDC

Input Duty Cycle

<135 MHz, VDD=3.3V

25

–

75

%

<135 MHz, VDD=2.5V

40

–

60

%

OUTDC

Output Duty Cycle

<135 MHz, VDD=3.3V

[2]

45

–

55

%

<135 MHz, VDD=2.5V

40

60

%

tr/f3.3

Rise, Fall Time (3.3V)

(Measured at: 0.8 to 2.0V)

[2]

High drive, CL = 15 pF, <135 MHz

–

–

0.75

ns

Std drive, CL = 15 pF, <170 MHz

–

–

1.5

ns

High drive, CL = 22 pF, <135 MHz

–

–

1.2

ns

Std drive, CL = 22 pF, <135 MHz

–

–

1.6

ns

High drive, CL = 30 pF, <100 MHz

–

–

1.5

ns

Std drive, CL = 30 pF, >100 MHz

–

–

2.5

ns

tr/f2.5

Rise, Fall Time (2.5)

(Measured at: 0.6 to 1.8V)

[2]

High drive, CL = 15 pF, <135 MHz

–

–

1.5

ns

Std drive, CL = 15 pF, <135 MHz

–

–

2.5

ns

High drive, CL = 22 pF, <135 MHz

–

–

1.3

ns

High drive, CL = 30 pF, >100 MHz

–

–

2.5

ns

t1

(Measured at VDD/2)

All outputs CL=0, 3.3V supply, 2.5 power

supply, standard drive

–

45

100

ps

All outputs CL=0, 2.5V power supply, high

drive

–

–

110

ps

t2

Delay Time, CLKIN Rising

Edge to CLKOUT Rising

Edge

(Measured at VDD/2)

[2]

PLL Bypass mode

1.5

–

4.4

ns

PLL enabled @ 3.3V

–100

–

100

ps

PLL enabled @2.5V

–200

–

200

ps

t3

Part-to-Part Skew

[2]

(Measured at VDD/2)

Measured at VDD/2. Any output to any

output, 3.3V supply

–

–

±150

ps

Measured at VDD/2. Any output to any

output, 2.5V supply

–

–

±300

ps