DLP9000 datasheet(13/56 Pages) TI1

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DLP9000

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DLPS036A – SEPTEMBER 2014 – REVISED OCTOBER 2015

7.5 Thermal Information

DLP9000

THERMAL METRIC (1)

FLS (CLGA)

UNIT

355 PINS

RθJA

Active area-to-case ceramic thermal resistance (max)

0.5

°C/W

(1)

The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate

heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the

Recommended Operating Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area;

although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical

systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in

this area can significantly degrade the reliability of the device. .

7.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS (1)

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

VCC = 3 V, IOH = –20 mA

2.4

VOL

Low level output voltage

VCC = 3.6, IOL = 15 mA

0.4

IIH

High–level input current (2) (3)

VCC = 3.6 V , VI = VCC

250

µA

IlL

Low level input current

VCC = 3.6 V, VI = 0

–250

µA

IOZ

High–impedance output current

VCC = 3.6 V

µA

CURRENT

DLP9000FLS VCC = 3.6 V, DCLK=400MHz

1600

ICC

DLP9000XFLS VCC = 3.6V, DCLK=480MHz

1850

Supply current (4)

DLP9000FLS VCCI = 3.6 V, DCLK=400MHz

985

ICCI

DLP9000XFLS VCCI = 3.6, DCLK=480MHz

1100

IOFFSET

VOFFSET = 8.75 V

Supply current (5)

IBIAS

VBIAS = 16.5 V

IRESET

VRESET = –10.5 V

ITOTAL

Supply current

DLP9000FLS Total Sum

2634

DLP9000XFLS Total Sum

3000

POWER

DLP9000FLS VCC = 3.6 V

5760

PCC

DLP9000XFLS VCC = 3.6 V

6660

DLP9000FLS VCCI = 3.6 V

3546

PCCI

Supply power dissipation

DLP9000XFLS VCCI = 3.6 V

3960

POFFSET

VOFFSET = 8.75 V

219

PBIAS

VBIAS = 16.5 V

231

PRESET

VRESET = –10.5 V

115

Supply power dissipation (6)

DLP9000FLS Total Sum, DCLK=400MHz

9871

PTOTAL

DLP9000XFLS Total Sum, DCLK=480MHz

11185

CAPACITANCE

Input capacitance

ƒ = 1 MHz

Output capacitance

ƒ = 1 MHz

Reset group capacitance

ƒ = 1 MHz ; 2560 × 50 micromirrors

230

290

MBRST(31:0)

(1)

All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for

proper DMD operation. VSS must also be connected.

(2)

Applies to LVCMOS input pins only. Does not apply to LVDS pins and MBRST pins.

(3)

LVCMOS input pins utilize an internal 18000

Ω passive resistor for pull-up and pull-down configurations. Refer to Pin Configuration and

Functions to determine pull-up or pull-down configuration used.

(4)

To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.

(5)

To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(6)

Total power on the active micromirror array is the sum of the electrical power dissipation and the absorbed power from the illumination

source. See the Micromirror Array Temperature Calculation.

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