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DLPC3435 Datasheet(PDF) 35 Page - Texas Instruments |
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DLPC3435 Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 59 page  x x x x x x x x x x x DMD_LS_RDATA DMD_LS_CLK DMD_LS_WDATA DMD_DEN_ARSTZ DMD_HS_WDATA_B_N DMD_HS_WDATA_B_P DMD_HS_WDATA_C_N DMD_HS_WDATA_C_P 600-MHz sub-LVDS DDR (High Speed) DMD_HS_WDATA_D_N DMD_HS_WDATA_D_P DMD_HS_CLK_N DMD_HS_CLK_P DMD_HS_WDATA_E_N DMD_HS_WDATA_E_P DMD_HS_WDATA_F_N DMD_HS_WDATA_F_P DMD_HS_WDATA_G_N DMD_HS_WDATA_G_P DMD_HS_WDATA_H_N DMD_HS_WDATA_H_P DMD_HS_WDATA_A_N DMD_HS_WDATA_A_P Sub-LVDS-DMD (Example DMD) .2 WVGA 854 x 480 display 120-MHz SDR (Low Speed) DLPC343x ASIC Leave Open for .2 WVGA DMD Leave Open for .2 WVGA DMD Leave Open for .2 WVGA DMD Leave Open for .2 WVGA DMD 35 DLPC3430, DLPC3435 www.ti.com DLPS038B – JULY 2014 – REVISED FEBRUARY 2016 Product Folder Links: DLPC3430 DLPC3435 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Figure 19. DLP2010 (.2 WVGA) DMD Interface Example (Mapping Option 1 Shown) 8.3.10 DLPC343x System Design Consideration – Application Notes System power regulation: It is acceptable for VDD_PLLD and VDD_PLLM to be derived from the same regulator as the core VDD, but to minimize the AC noise component they should be filtered as recommended in the PCB Layout Guidelines for Internal ASIC PLL Power. 8.3.11 Calibration and Debug Support The DLPC343x contains a test point output port, TSTPT_(7:0), which provides selected system calibration support as well as ASIC debug support. These test points are inputs while reset is applied and switch to outputs when reset is released. The state of these signals is sampled upon the release of system reset and the captured value configures the test mode until the next time reset is applied. Each test point includes an internal pulldown resistor, thus external pullups must be used to modify the default test configuration. The default configuration (x000) corresponds to the TSTPT_(7:0) outputs remaining tri-stated to reduce switching activity during normal operation. For maximum flexibility, an option to jumper to an external pullup is recommended for TSTPT_(2:0). Pullups on TSTPT_(6:3) are used to configure the ASIC for a specific mode or option. TI does not recommend adding pullups to TSTPT_(7:3) because this has adverse affects for normal operation. This external pullup is only sampled upon a 0-to-1 transition on the RESETZ input, thus changing their configuration after reset is released will not have any effect until the next time reset is asserted and released. Table 8 defines the test mode selection for one programmable scenario defined by TSTPT(2:0). |
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