DLPC3435 datasheet(45/59 Pages) TI1

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PLL_REFCLK_O

Crystal

PLL_REFCLK_I

DLPC3430, DLPC3435

www.ti.com

DLPS038B – JULY 2014 – REVISED FEBRUARY 2016

Product Folder Links: DLPC3430 DLPC3435

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Layout Guidelines (continued)

11.1.2 DLPC343x Reference Clock

The DLPC343x requires an external reference clock to feed its internal PLL. A crystal or oscillator can supply this

reference. For flexibility, the DLPC343x accepts either of two reference clock frequencies (see Table 10), but

both must have a maximum frequency variation of ±200 ppm (including aging, temperature, and trim component

variation). When a crystal is used, several discrete components are also required as shown in Figure 25.

CL = Crystal load capacitance (farads)

CL1 = 2 × (CL – Cstray_pll_refclk_i)

CL2 = 2 × (CL – Cstray_pll_refclk_o)

Where:

•

Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin associated with the ASIC pin

pll_refclk_i.

•

Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin associated with the ASIC pin

pll_refclk_o.

Figure 25. Required Discrete Components

11.1.2.1 Recommended Crystal Oscillator Configuration

Table 9. Crystal Port Characteristics

PARAMETER

NOM

UNIT

PLL_REFCLK_I TO GND capacitance

1.5

PLL_REFCLK_O TO GND capacitance

1.5

(1)

Temperature range of –30°C to +85°C

(2)

The crystal bias is determined by the ASIC's VCC_INTF voltage rail, which is variable (not the VCC18 rail).

Table 10. Recommended Crystal Configuration(1)(2)

PARAMETER

RECOMMENDED

UNIT

Crystal circuit configuration

Parallel resonant

Crystal type

Fundamental (first harmonic)

Crystal nominal frequency

24 or 16

MHz

Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity)

±200

PPM

Maximum startup time

1.0

Crystal equivalent series resistance (ESR)

120 max

Crystal load

RS drive resistor (nominal)

100

RFB feedback resistor (nominal)

CL1 external crystal load capacitor

See equation in Figure 25 notes

CL2 external crystal load capacitor

See equation in Figure 25 notes

PCB layout

A ground isolation ring around the

crystal is recommended

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