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TSM921 Datasheet(PDF) 17 Page - Silicon Laboratories |
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TSM921 Datasheet(HTML) 17 Page - Silicon Laboratories |
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17 / 20 page ![]() TSM921-TSM924 TSM921/24 Rev. 1.0 Page 17 PACKAGE OUTLINE DRAWING 8-Pin SOIC Package Outline Drawing (N.B., Drawings are not to scale) 1.27 TYP 0.33 - 0.51 4.80 - 5.00 3.73 - 3.89 0 - 8° 3.81 – 3.99 1 2 2 Notes: Does not include mold flash, protrusions or gate burns. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. Does not include inter-lead flash or protrusions. Inter-lead flash or protrusions shall not exceed 0.25 mm per side. Lead span/stand off height/coplanarity are considered as special characteristic (s). Controlling dimensions are in mm. This part is compliant with JEDEC specification MS-012 Lead span/stand off height/coplanarity are considered as Special characteristic. 1 2 LEADFARME THICKNESS 0.19 – 0.25 5.80 – 6.20 0.10 – 0.25 1.75 Max 0.10 Max 7' REF ALL SIDE 7' REF ALL SIDE 0.76 Max 0.66 Min 0.406 – 0.863 0.546 REF 0.48 Max 0.28 Min 45' Angle 0.25 5. 6. 1.32 – 1.52 GAUGE PLANE 3. 4. |
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