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DLPC3439 Datasheet(PDF) 39 Page - Texas Instruments |
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DLPC3439 Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 63 page  B C E D Video Video A A Pulse position changes on alternate subframes Both shutters off Next shutter on 39 DLPC3439 www.ti.com DLPS057B – NOVEMBER 2014 – REVISED JANUARY 2016 Product Folder Links: DLPC3439 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated NOTE: The period between DLPLink pulses alternates between the subframe period + D and the subframe period – D, where D is the delta period. Figure 23. 3D DLP Link Pulse Timing Table 7. 3D Link Nominal Timing Table HDMI SOURCE REFERENCE (Hz) 3D DMD SEQUENCE RATE (Hz) A (µs) B (µs) C (µs) D (µs) E (µs) 23.6 94.5 25 500 628 128 >2000 24.0 96 25 500 628 128 >2000 49.0 98 25 500 628 128 >2000 50.0 100 25 500 628 128 >2000 51.0 102 25 500 628 128 >2000 59.0 118 25 500 628 128 >2000 60.0 120 25 500 628 128 >2000 61.0 122 25 500 628 128 >2000 8.3.10 DMD (Sub-LVDS) Interface The DLPC3439 ASIC DMD interface consists of a HS 1.8-V sub-LVDS output only interface with a maximum clock speed of 600-MHz DDR and a LS SDR (1.8-V LVCMOS) interface with a fixed clock speed of 120 MHz. Table 8 shows how the 8 sub-LVDS lanes are configured for the DLP4710 (.47 1080p) DMD. Table 8. DLP4710 (.47 1080p) DMD – ASIC to 8-Lane DMD Pin Mapping DLPC3439 ASIC 8 LANE DMD ROUTING OPTIONS DMD PINS MASTER DLPC3439 CONFIGURATION Swap Control = x0 SLAVE DLPC3439 CONFIGURATION Swap Control = x2 HS_WDATA_D_P HS_WDATA_D_N HS_WDATA_E_P HS_WDATA_E_N Input DATA_p_0 Input DATA_n_0 HS_WDATA_C_P HS_WDATA_C_N HS_WDATA_F_P HS_WDATA_F_N Input DATA_p_1 Input DATA_n_1 HS_WDATA_B_P HS_WDATA_B_N HS_WDATA_G_P HS_WDATA_G_N Input DATA_p_2 Input DATA_n_2 HS_WDATA_A_P HS_WDATA_A_N HS_WDATA_H_P HS_WDATA_H_N Input DATA_p_3 Input DATA_n_3 HS_WDATA_H_P HS_WDATA_H_N HS_WDATA_A_P HS_WDATA_A_N Input DATA_p_4 Input DATA_n_4 HS_WDATA_G_P HS_WDATA_G_N HS_WDATA_B_P HS_WDATA_B_N Input DATA_p_5 Input DATA_n_5 HS_WDATA_F_P HS_WDATA_F_N HS_WDATA_C_P HS_WDATA_C_N Input DATA_p_6 Input DATA_n_6 HS_WDATA_E_P HS_WDATA_E_N HS_WDATA_D_P HS_WDATA_D_N Input DATA_p_7 Input DATA_n_7 |
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