A

B

C

D

E

F

G

H

1

2

3

4

5

6

DLPR910

www.ti.com

DLPS065A – SEPTEMBER 2015 – REVISED OCTOBER 2015

5 Pin Configuration and Functions

YVA Package

48-Pin DSBGA

Top View

I/O Type Descriptions

SUBSCRIPT

DESCRIPTION

P

Power

G

Ground

I

Input

O

Output

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

GND

A1

G

Ground

GND

A2

G

Ground

Output Enable/RESET (Open-Drain I/O). When Low, this input holds the address

counter reset and the DATA and CLKOUT outputs are placed in a high-impedance state.

OE/RESET

A3

I/O

This is a bidirectional open-drain pin that is held Low while the PROM completes the

internal power-on reset sequence. Polarity is not programmable. Pin must be pulled

High using an external 4.7-k

DNC

A4

Do Not Connect. Leave unconnected.

D6

A5

Do Not Connect. Leave unconnected.

D7

A6

Do Not Connect. Leave unconnected.

VCCINT

B1

P

Positive 1.8-V supply voltage for internal logic.

Positive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and

VCCO

B2

P

internal buffers.

Configuration clock input. Each rising edge on the CLK input increments the internal

CLK

B3

I

address counter. Pin must be pulled High and Low using an external 100-

Ω pull-up

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