DLPR910

DLPS065A – SEPTEMBER 2015 – REVISED OCTOBER 2015

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Pin Functions (continued)

PIN

I/O

DESCRIPTION

NAME

NO.

Chip Enable Input. When (CE ) is High, the device is put into low-power standby mode,

(CE)

B4

I

the address counter is reset, and the DATA and CLKOUT outputs are placed in a high

impedance state.

D5

B5

Do Not Connect. Leave unconnected.

GND

B6

G

Ground

BUSY

C1

Do Not Connect. Leave unconnected.

CLKOUT

C2

Do Not Connect. Leave unconnected.

DNC

C3

Do Not Connect. Leave unconnected.

DNC

C4

Do Not Connect. Leave unconnected.

D4

C5

Do Not Connect. Leave unconnected.

Positive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and

C6

P

internal buffers.

Configuration pin. The (CF) pin must be pulled High using an external 4.7-k

Ω pull-up

( CF)

D1

I

(CEO)

D2

Do Not Connect. Leave unconnected.

DNC

D3

Do Not Connect. Leave unconnected.

DNC

D4

Do Not Connect. Leave unconnected.

D3

D5

Do Not Connect. Leave unconnected.

Positive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and

D6

P

internal buffers.

E1

P

Positive 1.8-V supply voltage for internal logic.

TMS

E2

I

JTAG Mode Select Input. TMS has an internal 50-k

DNC

E3

Do Not Connect. Leave unconnected.

DNC

E4

Do Not Connect. Leave unconnected.

D2

E5

Do Not Connect. Leave unconnected.

TDO

E6

O

JTAG Serial Data Output. TDO has an internal 50-k

GND

F1

G

Ground

DNC

F2

Do Not Connect. Leave unconnected.

DNC

F3

Do Not Connect. Leave unconnected.

DNC

F4

Do Not Connect. Leave unconnected.

GND

F5

G

Ground

GND

F6

G

Ground

TDI

G1

I

JTAG Serial Data Input. TDI has an internal 50k-

DNC

G2

Do Not Connect. Leave unconnected.

REV_SEL0

G3

I

Revision Select [1:0] Inputs. When the (EN_EXT_SEL) is Low, the Revision Select pins

are used to select the design revision to be enabled. The Revision Select [1:0] inputs

have an internal 50-k

REV_SEL1

G4

I

Low using an external 10-k

Ω pull-down to Ground. The (REV_SEL1) pin must be

connected to Ground.

Positive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and

VCCO

G5

P

internal buffers.

VCCINT

G6

P

Positive 1.8-V supply voltage for internal logic.

GND

H1

G

Ground

Positive 3.3-V JTAG I/O supply voltage connected to the TDO output voltage driver and

VCCJ

H2

P

TCK, TMS and TDI input buffers.

JTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP controller and

TCK

H3

I

all the JTAG test and programming electronics.

External Selection Input. (EN_EXT_SEL) has an internal 50-k

Ω resistive pull- up to

(EN_EXT_SEL)

H4

I

D1

H5

Do Not Connect. Leave unconnected.

4

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