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MEC1322 Datasheet(PDF) 359 Page - Microchip Technology

Part # MEC1322
Description  Keyboard and Embedded Controller for Notebook PC
PDF  456 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MEC1322 Datasheet(HTML) 359 Page - Microchip Technology

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 2014 - 2015 Microchip Technology Inc.
DS00001719D-page 359
MEC1322
The maximum speed at which the BC-Link Master Interface can operate reliably depends on the drive strength of the
BC-Link BCM_CLK and BCM_DAT pins, as well as the nature of the connection to the Companion device (over ribbon
cable or on a PC board). The following table shows the recommended maximum speeds over a PC board as well as a
12 inch ribbon cable for selected drive strengths. The frequency is set with the BC-Link Clock Select Register.
31.6
Host Interface
The registers defined for the BC-Link Master Interface are accessible by the various hosts as indicated in Section 31.11,
"EC-Only Registers".
31.7
Power, Clocks and Reset
31.7.1
POWER DOMAINS
31.7.2
CLOCK INPUTS
31.7.3
RESETS
31.8
Interrupts
This section defines the Interrupt Sources generated from this block.
TABLE 31-2:
BC-LINK MASTER PIN DRIVE STRENGTH VS. FREQUENCY
Pin Drive
Strength
Max Freq
on PC Board
Min Value in
BC-Link Clock Select
Register
Max Freq
over Ribbon cable
Min Value in
BC-Link
Clock Select Register
16mA
24Mhz
1
16Mhz
2
TABLE 31-3:
POWER SOURCES
Name
Description
VCC1
The logic and registers implemented in this block are powered by this
power well.
TABLE 31-4:
CLOCK INPUTS
Name
Description
48 MHz Ring Oscillator
This is the clock source for Keyboard Scan Interface logic.
TABLE 31-5:
RESET SIGNALS
Name
Description
VCC1_RESET
This signal resets all the registers and logic in this block to their default
state.
TABLE 31-6:
EC INTERRUPTS
Source
Description
BCM_INT Busy
Interrupt request to the Interrupt Aggregator, generated from the status
event BUSYdefined in the BC-Link Status Register.
BCM_INT Err
Interrupt request to the Interrupt Aggregator, generated from the status
event defined in the BC-Link Status Register.
BC_INT_N_WK
Wake-up request to the Interrupt Aggregator’s wake-up interface for BC-
Link Master port.
In order to enable BC-Link wakeup interrupts, the pin control registers for
the BC_INT# pin must be programmed to Input, Falling Edge Triggered,
non-inverted polarity detection.



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