MEC1322 datasheet(362/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 362

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31.11.1

BC-LINK STATUS REGISTER

31.11.2

BC-LINK ADDRESS REGISTER

Offset

00h

Bits

Description

Type

Default

Reset

Event

31:4 Reserved

7 RESET

When this bit is ‘1’the BC_Link Master Interface will be placed in

reset and be held in reset until this bit is cleared to ‘0’. Setting

RESET to ‘1’ causes the BUSY bit to be set to ‘1’. The BUSY

remains set to ‘1’ until the reset operation of the BC Interface is com-

pleted, which takes approximately 48 BC clocks.

The de-assertion of the BUSY bit on reset will not generate an inter-

rupt, even if the BC_BUSY_CLR_INT_EN bit is ‘1’. The BUSY bit

must be polled in order to determine when the reset operation has

completed.

R/W

VCC1_R

ESET

6BC_ERR

This bit indicates that a BC Bus Error has occurred. If an error

occurs this bit is set by hardware when the BUSY bit is cleared. This

bit is cleared when written with a ’1’. An interrupt is generated If this

bit is ‘1’ and BC_ERR_INT_EN bit is ‘1’.

Errors that cause this interrupt are:

• Bad Data received by the BASE (CRC Error)

• Time-out caused by the COMPANION not responding.

All COMPANION errors cause the COMPANION to abort the opera-

tion and the BASE to time-out.

R/WC

VCC1_R

ESET

5 BC_ERR_INT_EN

This bit is an enable for generating an interrupt when the BC_ERR

bit is set by hardware. When this bit is ‘1’, the interrupt signal is

enabled. When this bit is ‘0’, the interrupt is disabled.

R/W

VCC1_R

ESET

4 BC_BUSY_CLR_INT_EN

This bit is an enable for generating an interrupt when the BUSY bit in

this register is cleared by hardware. When this bit is set to ‘1’, the

interrupt signal is enabled. When the this bit is cleared to ‘0’, the inter-

rupt is disabled. When enabled, the interrupt occurs after a BC Bus

read or write.

R/W

VCC1_R

ESET

3:1 Reserved

0BUSY

This bit is asserted to ‘1’ when the BC interface is transferring data

and on reset. Otherwise it is cleared to ‘0’. When this bit is cleared

by hardware, an interrupt is generated if the BC_BUSY_CL-

R_INT_EN bit is set to ‘1’.

VCC1_R

ESET

Offset

04h

Bits

Description

Type

Default

Reset

Event

31:8 Reserved

7:0 ADDRESS

Address in the Companion for the BC-Link transaction.

R/W

VCC1_R

ESET

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