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MEC1322 Datasheet(PDF) 363 Page - Microchip Technology |
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MEC1322 Datasheet(HTML) 363 Page - Microchip Technology |
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363 / 456 page ![]() 2014 - 2015 Microchip Technology Inc. DS00001719D-page 363 MEC1322 31.11.3 BC-LINK DATA REGISTER 31.11.4 BC-LINK CLOCK SELECT REGISTER Offset 08h Bits Description Type Default Reset Event 31:8 Reserved R - - 7:0 DATA As described in Section 31.10.1, "BC-Link Master READ Operation" and Section 31.10.2, "BC-Link Master WRITE Operation", this regis- ter hold data used in a BC-Link transaction. R/W 0h VCC1_R ESET Offset 0Ch Bits Description Type Default Reset Event 31:8 Reserved R - - 7:0 DIVIDER The BC Clock is set to the Master Clock divided by this field, or 48MHz/ (Divider +1). The clock divider bits can only can be changed when the BC Bus is in soft RESET (when either the Reset bit is set by software or when the BUSY bit is set by the interface). Example settings for DIVIDER are shown in Table 31-9, "Example Frequency Settings". R/W 4h VCC1_R ESET TABLE 31-9: EXAMPLE FREQUENCY SETTINGS Divider Frequency 0 48MHz 1 24MHz 2 16MHz 3 12MHz 49.6MHz 15 2.18MHz 2A 1.12MHz |
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