MEC1322 datasheet(367/456 Pages) MICROCHIP

Part #	MEC1322

Description	Keyboard and Embedded Controller for Notebook PC

PDF	456 Pages

Scroll/Zoom	100%

Manufacturer	MICROCHIP [Microchip Technology]

Direct Link	http://www.microchip.com

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 2014 - 2015 Microchip Technology Inc.

DS00001719D-page 367

MEC1322

32.11.2

DEBUG CONTROL REGISTER

Offset

04h

Bits

Description

Type

Default

Reset

Event

7 Reserved

6:4 IP_DELAY

Inter-packet Delay. The delay is in terms of TFDP Debug output

clocks. A value of 0 provides a 1 clock inter-packet period, while a

value of 7 provides 8 clocks between packets:

R/W

000b

VCC1_R

ESET

3:2 DIVSEL

Clock Divider Select. The TFDP Debug output clock is determined

by this field, according to Table 32-7, "TFDP Debug Clocking":

R/W

00b

VCC1_R

ESET

1 EDGE_SEL

1= Data is shifted out on the falling edge of the debug clock

0= Data is shifted out on the rising edge of the debug clock (Default)

R/W

VCC1_R

ESET

0EN

Enable.

1=Clock enabled

0=Clock is disabled (Default)

R/W

VCC1_R

ESET

TABLE 32-7:

TFDP DEBUG CLOCKING

divsel

TFDP Debug Clock

24 MHz

12 MHz

6 MHz

Reserved

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