MEC1322 datasheet(369/456 Pages) MICROCHIP

369 / 456 page

 2014 - 2015 Microchip Technology Inc.

DS00001719D-page 369

MEC1322

33.6

Host Interface

The registers defined for the Trace FIFO Debug Port are accessible by the various hosts as indicated in Section 33.11,

"EC-Only Registers".

33.7

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

33.7.1

POWER DOMAINS

33.7.2

CLOCK INPUTS

33.7.3

RESETS

33.8

Interrupts

33.9

Low Power Modes

The ADC may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.

The ADC is designed to conserve power when it is either sleeping or disabled. It is disabled via the Activate Bit and

sleeps when the ADC_SLEEP_EN signal is asserted. The sleeping state only controls clocking in the ADC and does

not power down the analog circuitry. For lowest power consumption, the ADC Activate bit must be set to ‘0.’

TABLE 33-2:

POWER SOURCES

Name

Description

VCC1

This power well sources the registers tn this block.

AVCC

This power well sources of the logic in this block, except where noted.

AVSS

This is the ground signal for the block.

TABLE 33-3:

CLOCK INPUTS

Name

Description

1.2MHz

This derived clock signal drives selected logic (1.2 MHz clock with a 50%

duty cycle).

TABLE 33-4:

RESET SIGNALS

Name

Description

VCC1_RESET

This reset signal resets all of the registers and logic in this block.

TABLE 33-5:

EC INTERRUPTS

Source

Description

ADC_Single_Int

Interrupt signal from ADC controller to EC for Single-Sample ADC con-

version.

ADC_Repeat_Int

Interrupt signal from ADC controller to EC for Repeated ADC conversion.

Note:

The ADC VREF must be powered down in order to get the lowest deep sleep current. The ADC VREF

Power down bit, ADC_VREF_PD_REF is in the EC Subsystem Registers ADC VREF PD on page 381.

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