MEC1322 datasheet(370/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 370

 2014 - 2015 Microchip Technology Inc.

33.10 Description

The MEC1322 features a five channel successive approximation Analog to Digital Converter. The ADC architecture fea-

tures excellent linearity and converts analog signals to 10 bit words. Conversion takes less than 12 microseconds per

10-bit word. The five channels are implemented with a single high speed ADC fed by a five input analog multiplexer.

The multiplexer cycles through the five voltage channels, starting with the lowest-numbered channel and proceeding to

the highest-number channel, selecting only those channels that are programmed to be active.

The input range on the voltage channels spans from 0V to the internal voltage reference. With an internal voltage ref-

erence of 3.0V, this provides resolutions of 2.9mV. The range can easily be extended with the aid of resistor dividers.

The accuracy of any voltage reading depends on the accuracy and stability of the voltage reference input.

The ADC conversion cycle starts either when the Start_Single bit in the ADC to set to 1 or when the ADC Repeat Timer

counts down to 0. When the Start_Single is set to 1 the conversion cycle converts channels enabled by configuration

bits in the ADC Single Register. When the Repeat Timer counts down to 0 the conversion cycle converts channels

enabled by configuration bits in the ADC Repeat Register. When both the Start_Single bit and the Repeat Timer request

conversions the Start_Single conversion is completed first.

Conversions always start with the lowest-numbered enabled channel and proceed to the highest-numbered enabled

channel.

33.10.1

REPEAT MODE

• Repeat Mode will start a conversion cycle of all ADC channels enabled by bits Rpt_En[4:0] in the ADC Repeat

ter.

FIGURE 33-2:

ADC BLOCK DIAGRAM

Note:

The ADC pins are 3.3V tolerant.

Note:

If software repeatedly sets Start_Single to 1 at a rate faster than the Repeat Timer count down interval, the

conversion cycle defined by the ADC Repeat Register will not be executed.

ADC BLOCK

ADC Reading Registers

ADC_Single_Int

Latch

Control

Logic

10-bit reading value

reading

Host Interface

MUX

ADC

Control

Analog Inputs

(

VREF

ADC_Repeat_Int

ADC_SLEEP_EN

ADC_CLK_REQ

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