MEC1322 datasheet(374/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 374

 2014 - 2015 Microchip Technology Inc.

33.11.4

ADC SINGLE REGISTER

The ADC Single Register is used to control which ADC channel is captured during a Single-Sample conversion cycle

initiated by the Start_Single bit in the ADC Control Register.

APPLICATION NOTE:

Do not change the bits in this register in the middle of a conversion cycle to insure proper

operation.

33.11.5

ADC REPEAT REGISTER

The ADC Repeat Register is used to control which ADC channels are captured during a repeat conversion cycle initiated

by the Start_Repeat bit in the ADC Control Register.

33.11.6

ADC CHANNEL READING REGISTERS

All 5 ADC channels return their results into a 32-bit reading register. In each case the low 10 bits of the reading register

return the result of the Analog to Digital conversion and the upper 22 bits return 0. Table 33-7, “Analog to Digital Con-

verter Register Summary,” on page 371 shows the addresses of all the reading registers.

Offset

0Ch

Bits

Description

Type

Default

Reset

Event

31:5 RESERVED

RES

4:0 Single_En[4:0]

0: single cycle conversions for this channel are disabled

1: single cycle conversions for this channel are enabled

Each bit in this field enables the corresponding ADC channel when a

single cycle of conversions is started when the Start_Single bit in the

ADC Control Register is written with a 1.

R/W

00h

VCC1_R

ESET

Offset

10h

Bits

Description

Type

Default

Reset

Event

31:5

RESERVED

RES

4:0

Rpt_En[4:0]

0: repeat conversions for this channel are disabled

1: repeat conversions for this channel are enabled

Each bit in this field enables the corresponding ADC channel for

each pass of the Repeated ADC Conversion that is controlled by bit

Start_Repeat in the ADC Control Register.

R/W

00h

VCC1_R

ESET

Note:

The ADC Channel Reading Registers access require single 16, or 32 bit reads; i.e., two 8 bit reads cannot

ensure data coherency.

Offset

See Table 33-7, "Analog to Digital Converter Register Summary"

Bits

Description

Type

Default

Reset

Event

31:10 RESERVED

RES

9:0 ADCx_[9:0]

This read-only field reports the 10-bit output reading of the Input

ADCx.

R/W

000h

VCC1_R

ESET

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