MEC1322 datasheet(372/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 372

 2014 - 2015 Microchip Technology Inc.

33.11.1

ADC CONTROL REGISTER

The ADC Control Register is used to control the behavior of the Analog to Digital Converter.

Offset

00h

Bits

Description

Type

Default

Reset

Event

31:8 RESERVED

RES

7 Single_Done_Status

This bit is cleared when it is written with a 1. Writing a 0 to this bit

has no effect.

This bit can be used to generate an EC interrupt.

0: ADC single-sample conversion is not complete. This bit is cleared

whenever an ADC conversion cycle begins for a single conversion

cycle.

1: ADC single-sample conversion is completed. This bit is set to 1

when all enabled channels in the single conversion cycle.

R/WC

VCC1_R

ESET

6 Repeat_Done_Status

This bit is cleared when it is written with a 1. Writing a 0 to this bit

has no effect.

This bit can be used to generate an EC interrupt.

0: ADC repeat-sample conversion is not complete. This bit is cleared

whenever an ADC conversion cycle begins for a repeating conver-

sion cycle.

1: ADC repeat-sample conversion is completed. This bit is set to 1

when all enabled channels in a repeating conversion cycle com-

plete.

R/WC

VCC1_R

ESET

5 RESERVED

RES

4 Soft Reset

1: writing one causes a reset of the ADC block hardware (not the

registers)

0: writing zero takes the ADC block out of reset

R/W

VCC1_R

ESET

3 Power_Saver_Dis

0: Power saving feature is enabled. The Analog to Digital Converter

controller powers down the ADC between conversion sequences.

1: Power saving feature is disabled.

R/W

VCC1_R

ESET

2 Start_Repeat

0: The ADC Repeat Mode is disabled. Note: This setting will not ter-

minate any conversion cycle in process, but will inhibit any further

periodic conversions.

1: The ADC Repeat Mode is enabled. This setting will start a conver-

sion cycle of all ADC channels enabled by bits Rpt_En[4:0] in the

ADC Repeat Register.

R/W

VCC1_R

ESET

1 Start_Single

0: The ADC Single Mode is disabled.

1: The ADC Single Mode is enabled. This setting starts a single con-

version cycle of all ADC channels enabled by bits Single_En[4:0] in

the ADC Single Register.

Note:

This bit is self-clearing

R/W

VCC1_R

ESET

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