MEC1322 datasheet(373/456 Pages) MICROCHIP

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DS00001719D-page 373

MEC1322

33.11.2

ADC DELAY REGISTER

The ADC Delay register determines the delay from setting Start_Repeat in the ADC Control Register and the start of a

conversion cycle. This register also controls the interval between conversion cycles in repeat mode.

33.11.3

ADC STATUS REGISTER

The ADC Status Register indicates whether the ADC has completed a conversion cycle.

0 Activate

0: The ADC is disabled and placed in its lowest power state. Note:

Any conversion cycle in process will complete before the block is

shut down, so that the reading registers will contain valid data but no

new conversion cycles will begin.

1: ADC block is enabled for operation. Start_Single or Start_Repeat

can begin data conversions by the ADC. Note: A reset pulse is sent

to the ADC core when this bit changes from 0 to 1.

R/W

VCC1_R

ESET

Offset

04h

Bits

Description

Type

Default

Reset

Event

31:16 Repeat_Delay[15:0]

This field determines the interval between conversion cycles when

Start_Repeat is 1. The delay is in units of 40

μs. A value of 0 means

no delay between conversion cycles, and a value of 0xFFFF means

a delay of 2.6 seconds.

This field has no effect when Start_Single is written with a 1.

R/W

0000h

VCC1_R

ESET

15:0 Start_Delay[15:0]

This field determines the starting delay before a conversion cycle is

begun when Start_Repeat is written with a 1. The delay is in units of

μs. A value of 0 means no delay before the start of a conversion

cycle, and a value of 0xFFFF means a delay of 2.6 seconds.

This field has no effect when Start_Single is written with a 1.

R/W

0000h

VCC1_R

ESET

Offset

08h

Bits

Description

Type

Default

Reset

Event

31:5 RESERVED

RES

4:0 ADC_Ch_Status[4:0]

All bits are cleared by being written with a ‘1’.

0: conversion of the corresponding ADC channel is not complete

1: conversion of the corresponding ADC channel is complete

Note: for enabled single cycles, the Single_Done_Status bit in the

ADC Control Register is also set after all enabled channel conver-

sion are done; for enabled repeat cycles, the Repeat_Done_Status

in the ADC Control Register is also set after all enabled channel con-

version are done.

R/WC

00h

VCC1_R

ESET

Offset

00h

Bits

Description

Type

Default

Reset

Event

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