MEC1322 datasheet(360/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 360

 2014 - 2015 Microchip Technology Inc.

31.9

Low Power Modes

The BC-Link Master Interface automatically enters a low power mode whenever it is not active (that is, whenever the

BUSY bit in the BC-Link Status Register is ‘0’). When the interface is in a low-power mode it will not prevent the chip

from entering a sleep state. When the interface is active it will inhibit the chip sleep state until the interface has re-

entered its low power mode.

31.10 Description

31.10.1

BC-LINK MASTER READ OPERATION

The BC-Link Read protocol requires two reads of the BC-Link Data Register. The two reads drive a two state-state

machine: the two states are Read#1 and Read#2. The Read#1 of the Data Register starts the read protocol on the BC-

Link pins and sets the BUSY bit in the BC-Link Status Register. The contents of the data read during Read#1 by the EC

is stale and is not to be used. After the BUSY bit in the BC-Link Status Register autonomously clears to ‘0’, the Read#2

of the Data Register transfers the data read from the peripheral/BC-Link companion chip to the EC.

Software starts by checking the status of the BUSY bit in the Status Register. If the BUSY bit is ‘0’, proceed. If

BUSY is ‘1’, firmware must wait until it is ‘0’.

Software writes the address of the register to be read into the BC-Link Address Register.

Software then reads the Data Register. This read returns random data. The read activates the BC-Link Master

state machine to transmit the read request packet to the BC-Link companion. When the transfer initiates, the

hardware sets the BUSY bit to a ‘1’.

The BC-Link Companion reads the selected register and transmits the read response packet to the BC-Link Mas-

ter. The Companion will ignore the read request if there is a CRC error; this will cause the Master state machine

to time-out and issue a BC_ERR Interrupt.

FIGURE 31-2:

BC-LINK MASTER BLOCK DIAGRAM

BC Bus Master IP

BCM_CLK

BCM_DAT

BCM_INT#

BC Status / Control

BC Data

BC Address

External Pin interface

EC IF

Registers

Clock

Divider

Bits

BC_BUSY_CLR

BC_ERR

Clock

Generator

MCLK/2

MCLK/4

MCLK/8

∗

MCLK/

MCLK=48MHz Ring Oscillator

∗

MCLK/

Divider

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