L9663 datasheet(83/104 Pages) STMICROELECTRONICS

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L9663

Communication interface

103

5.2.3

Frame definition

Global status bits (standard mode)

Global status bits (address multiplexing mode)

Type: R

The global status bits are shifted out on the MISO line on every SPI access. They provide

information about the current device status.

5.2.4

Communication frames

In the following frames, all fields are written with MSB at left side and 'X' represents a "don't

care" value.

The bit RW is used to select the operation type on the internal register: read (RW=0), write

(RW=1).

CRC on MOSI is calculated over bits 31:5. CRC on MISO is:

CRC from the sensor

CRC calculated over bits 26:3

depending on GCR1[1].

SPIE

FSR1

FSR2

RSTB

PROG

GSB

RSTB

PROG

GSB

Bit Description

[31] SPIE: SPI error

The SPIE bit is a logical OR combination of errors related to wrong SPI communication (wrong

SCLK count, wrong CRC, wrong SPI operation). It is also reported as SR1[12] bit and it is

automatically cleared when this register is read.

[30] FSR1: Fault status register 1 flag

The FSR1 bit is set to '1' if at least one of the bits SR1[11:0] is active.

[29] FSR2: Fault status register 2 flag

The FSR2 bit is set to '1' if at least one of the bits SR2[14:8] or SR2[6:0] is active.

[28] RSTB: Reset bit

The RSTB bit indicates a device reset (POR, RESETN or SW_RESET). In case this bit is set,

all internal Control Registers are set to their default values and kept in that state until the bit is

cleared. It is automatically cleared by any valid SPI communication.

[27] PROG: End of programming

The EOP bit indicates the end of the device programming phase (PROG registers).

[26] GSB: Global Status Bit

The GSB bit is a logical OR combination of Bit 31 to Bit 27 and buffer empty error bit. This

stands also for address multiplexing mode.

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