L9663 datasheet(29/104 Pages) STMICROELECTRONICS

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L9663

Satellite interface

103

In case of PSI5 v2.x, the length of the data region can vary between k = 10 … 28 bits, with

1-bit granularity. The data region can be split into the following fields and regions:



Signal payload region 1 with data bits A0 … A[n-1] (scalable n = 10…24 with 1-bit

granularity)



Signal payload region 2 with data bits B0 … B[m-1] (scalable m = 0…12 with 1-bit

granularity)



Sensor status E0.. E[r-1] (optional r = 0, 1 or 2 bit)

–

This optional status bit can be used to show that the data of the current frame are

faulty.



Frame control, type of frame F0, …F[q-1] (optional q = 0, 1, 2, 3 or 4 bit)

–

This frame control can be used to number the frames which are sent after a sync

pulse.



Serial (slow) messaging channel (optional) M0, M1 (optional 0 or 2 bit)

Time slot monitoring

The time slot monitoring is active only in synchronous mode.

The time slot monitoring is required to check if the sensors connected to the transceiver

work properly in terms of timing, i.e. if they are sending data frames within their defined time

slot.

Basic features:



3 configurable modes



Failure bit

During a synchronous pulse period (TSYNC), a maximum number of 6 frames can be

configured. Each frame has its own time slot, to be configured through dedicated

configuration registers. The registers contain the reference time needed to check if the

sensor data is transmitted during the defined time slot.

The resolution of time slots is 1 μs. The time slot monitoring timings are applied starting

from the internal sync pulse trigger. This internal trigger falls td_SPI (or td_SYNC, depending

on sync pulse trigger configuration) after the external one (via SPI or SYNC pin).

Three different configurations for the time slot monitoring are available:



Standard configuration: monitoring the correct start and end time of a unique frame

within a time slot



Simple configuration: monitoring only the end time of a frame within a time slot



No monitoring configuration: monitoring is disabled and data are stored in successive

slots.

The time slot monitoring can be activated/deactivated separately for each interface

(registers CHx_CR1, bits TSMx_SEL).

In case of standard configuration, the IC accepts as valid frame in a timeslot only a frame

which starts and ends within its timeslot; if more than one valid frame is received within its

timeslot, only the last one received is kept.

On the other side, in case frames span across slots, the frame is discarded and the error

code 1FC (timing violation) is stored in the correspondent buffer; in this case the decoder is

reset at every slot start. After this reset if a frame was being decoded, a slot error is set in

the previous slot but no slot error is set. Then the Manchester FSM after reset checks again

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