DP83867CS datasheet(101/114 Pages) TI1

101 / 114 page

DP83867CS, DP83867IS, DP83867E

www.ti.com

SNLS504 – OCTOBER 2015

10.2.2 Detailed Design Procedure

10.2.2.1 MAC Interface

The Media Independent Interface (SGMII / RGMII) connects the DP83867 to the Media Access Controller (MAC).

The MAC may in fact be a discrete device, integrated into a microprocessor, CPU or FPGA.

10.2.2.1.1

SGMII Layout Guidelines

•

All SGMII connections should be AC coupled via an 0.1µF capacitor. Series capacitors should be 0.1uF and

the size should be 0402 or smaller.

•

SGMII signals are differential signals.

•

Traces should be routed with 100-

Ω differential impedance.

•

Skew matching within a pair should be less than 5pS, which correlates to 30mil for standard FR4.

•

There is no requirement to match the TX pair to the RX pair.

•

SGMII signals should be routed on the same layer.

•

Pairs should be referenced to parallel ground plane.

•

When operating in 6-wire mode, the RX pair must match the Clock pair to within 5pS, which correlates to

30mil for standard FR4.

10.2.2.1.2

RGMII Layout Guidelines

•

RGMII signals are single-ended signals.

•

Traces should be routed with impedance of 50

Ω to ground.

•

Skew between TXD[3:0] lines should be less than 11ps, which correlates to 60mil for standard FR4.

•

Skew between RXD[3:0] lines should be less than 11ps, which correlates to 60mil for standard FR4.

•

Keep trace lengths as short as possible, less than 2 inches recommended, less than 6 inches maximum

length.

•

Configurable clock skew for GTX_CLK and RX_CLK.

–

Clock skew for RX and TX paths can be optimized independently.

–

Clock skew is adjustable in 0.25ns increments (via register).

10.2.2.2 Media Dependent Interface (MDI)

The Media Dependent Interface (MDI) connects the DP83867 to the transformer and the Ethernet network.

10.2.2.2.1

MDI Layout Guidelines

•

MDI traces should be 50

Ω to ground or 100 Ω differential controlled impedance.

•

Route MDI traces to transformer on the same layer.

•

Use a metal shielded RJ-45 connector, and connect the shield to chassis ground.

•

Use magnetics with integrated common mode choking devices.

•

Void supplies and ground beneath magnetics.

•

Do not overlap the circuit and chassis ground planes, keep them isolated. Instead, make chassis ground an

isolated island and make a void between the chassis and circuit ground. Connecting circuit and chassis

planes using a size 1206 resistor and capacitor on either side of the connector is a good practice.

Submit Documentation Feedback

101

DP83867CS Datasheet(PDF) 101 Page - Texas Instruments

DP83867CS Datasheet(HTML) 101 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL