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DP83867CS Datasheet(PDF) 104 Page - Texas Instruments

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Part # DP83867CS
Description  High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver
PDF  114 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DP83867CS Datasheet(HTML) 104 Page - Texas Instruments

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DP83867CS, DP83867IS, DP83867E
SNLS504 – OCTOBER 2015
www.ti.com
12 Layout
12.1 Signal Traces
PCB traces are lossy and long traces can degrade the signal quality. Traces should be kept short as possible.
Unless mentioned otherwise, all signal traces should be 50
Ω single ended impedance. Differential traces should
be 50
Ω single ended and 100Ω differential. Care should be taken that the impedance is constant throughout.
Impedance discontinuities will cause reflections leading to EMI & signal integrity problems. Stubs should be
avoided on all signal traces, especially the differential signal pairs. See Figure 28
Within the differential pairs, the trace lengths should be run parallel to each other and matched in length.
Matched lengths minimize delay differences, avoiding an increase in common mode noise and increased EMI.
Length matching is also important on MAC interface. All Transmit signal traces should be length matched to each
other and all Receive signal traces should be length matched to each other.
Ideally, there should be no crossover or via on the signal paths. Vias present impedance discontinuities and
should be minimized. Route an entire trace pair on a single layer if possible.
Figure 28. Avoiding Stubs in a Differential Signal Pair
Signals on different layers should not cross each other without at least one return path plane between them.
Coupling between traces is also an important factor. Unwanted coupling can cause cross talk problems.
Differential pairs on the other hand, should have a constant coupling distance between them.
For convenience & efficient layout process, start by routing the critical signals first.
12.2 Return path
A general best practice is to have a solid return path beneath all signal traces. This return path can be a
continuous ground or DC power plane. Reducing the width of the return path width can potentially affect the
impedance of the signal trace. This effect is more prominent when the width of the return path is comparable to
the width of the signal trace. Breaks in return path beneath the signal traces should be avoided at all cost. A
signal crossing a plane split may cause unpredictable return path currents and would likely impact signal quality
as well, potentially creating EMI problems. See Figure 29
104
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