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SN65DP141 Datasheet(PDF) 21 Page - Texas Instruments |
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SN65DP141 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 32 page ![]() 21 SN65DP141 www.ti.com SLLSES6 – FEBRUARY 2016 Product Folder Links: SN65DP141 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 8.5.7 Register 0x08 (Channel 2 Control Settings) (offset = 00000000) [reset = 00000000] Figure 23. Register 0x08 (Channel 2 Control Settings) 7 6 5 4 3 2 1 0 RSVD EQ Setting<2> EQ Setting<1> EQ Setting<0> TX_GAIN EQ_DC_GAIN RX_GAIN<1> RX_GAIN<0> R/W R/W R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 10. Register 0x08 (Channel 2 Control Settings) Bit Field Type Reset Description 7 RSVD R/W 0 6 EQ Setting<2> R/W 0 Equalizer adjustment setting: 000 = Minimum equalization setting 111 = Maximum equalization setting 5 EQ Setting<1> R/W 0 4 EQ Setting<0> R/W 0 3 TX_GAIN R/W 0 Channel [2] TX_DC_GAIN control: 0 = Set 0 dB DC gain for transmitter 1 = Set 6 dB DC gain for transmitter 2 EQ_DC_GAIN R/W 0 Channel [2] EQ DC gain: 0 = Set EQ DC gain to -6 dB 1 = Set EQ DC gain to -0 dB 1 RX_GAIN<1> R/W 0 Equivalent to RX_GAIN control pin for channel [2]. 00: RX_GAIN = Low 01: RX_GAIN = HiZ 11: RX_GAIN = High 0 RX_GAIN<0> R/W 0 8.5.8 Register 0x09 (Channel 2 Enable Settings) (offset = 00000000) [reset = 00000000] Figure 24. Register 0x09 (Channel 2 Enable Settings) 7 6 5 4 3 2 1 0 DRV_PEAK EQ_EN DRV_EN R R R R R R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 11. Register 0x09 (Channel 2 Enable Settings) Bit Field Type Reset Description 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 DRV_PEAK R/W 0 Channel [2] driver peaking: 0 = Disables driver Peaking 1 = Enables driver 6 db AC Peaking 1 EQ_EN R/W 0 Channel [2] driver stage enable: 0 = Enable 1 = Disable 0 DRV_EN R/W 0 Channel [2] driver stage enable: 0 = Enable 1 = Disable |
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