4 Bit Register

1 Bit Register

1 Bit Register

VCC

200K

50

50

VBB

50

50

Band-Gap Voltage

Reference and Bias

Current Generation

Power-OnReset

OUT[3:0]_P

I2C_EN

2-Wire Interface and Control Logic

I2C_EN

EQ0/ADD0

EQ1/ADD1

EQ_MODE/ADD2

6 Bit Register

3 Bit Register

General Setting

200K

1.2K

200K

200K

200K

GND

IN[3:0]_P

DRV_PK#/SCL

SDA

PWD#

VOD/CS

GAIN

Input Buffer with

Selectable Equalizer

Output Driver

VCC

Power-On

Reset

OUT[3:0]_P

2 Bit Register

DC Gain

EQ Control

Channel Enable

VOD Swing

AC Gain

SDA

PWD#

VOD/CS

GAIN

DRV_PK#/SCL

EQ1/ADD1

EQ0/ADD0

EQ_MODE/ADD2

IN[3:0]_N

13

SN65DP141

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SLLSES6 – FEBRUARY 2016

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8 Detailed Description

8.1 Overview

The SN65DP141 is an asynchronous, protocol-agnostic, low latency, four-channel linear equalizer optimized for

use up to 12 Gbps. The characteristics of this device make it transparent to DisplayPort (DP) link training, it

supports all the available DP bit rates from RBR to HBR3 (1.6 Gbps, 2.7 Gbps, 5.4 Gbps and 8.1 Gbps

respectively). Additionally, the SN65DP141 is configurable to a trace or cable mode, and hence improves its

performance depending on the type of channel it is being used. Its transparency to the DP link training makes the

SN65DP141 a position independent device, suitable for source/sink or cable applications, effectively providing a

“negative loss” component to the overall link budget, in order to compensate the signal degradation over the

channel.

activation, equalization, gain, dynamic range.

8.2 Functional Block Diagram