INx_P

INx_N

OUTx_P

OUTx_N

TX_GAIN(TX_DC_GAIN)

EQUALIZATION(EQ_AC_GAIN)

RX_GAIN(EQ_DC_GAIN)

0dB or -6dB

Up to 15dB

0dB or 6dB

14

SN65DP141

SLLSES6 – FEBRUARY 2016

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8.3 Feature Description

8.3.1

DC and AC Independent Gain Control

Besides the functional block diagram, the behavior of the SN65DP141 can be described as it is shown in

Figure 16; where the input stage first applies a DC gain (0 dB or –6 dB), and then equalizes the signal, which is

driven to the output stage, where the SN65DP141 applies an output DC gain (0 dB or 6 dB).

Figure 16. DP141 Signal Chain Gain Control

8.3.2 Two-Wire Serial Interface and Control Logic

The SN65DP141 uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCL, are

driven, respectively, by the serial data and serial clock from a microcontroller, for example. The SDA and SCK

pins require external 10 k

Ω pull-ups to VCC.

The 2-wire interface allows write access to the internal memory map to modify control registers and read access

to read out control and status signals. The SN65DP141 is a slave device only which means that it cannot initiate

a transmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. The

master device provides the clock signal as well as the START and STOP commands. The protocol for a data

transmission is as follows:

1. START command

2. 7 bit slave address (0000ADD [2:0]) followed by an eighth bit which is the data direction bit (R/W). A zero

indicates a WRITE and a 1 indicates a READ. The ADD [2:0] address bits change with the status of the

ADD2, ADD1, and ADD0 device pins, respectively. If the pins are left floating or pulled down, the 7 bit slave

address is 0000000.

3. 8-bit register address

4. 8-bit register data word

5. STOP command

Switching Characteristics.

8.3.3 Bus Idle

Both SDA and SCL lines remain HIGH

8.3.4 Start Data Transfer

A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START

condition (S). Each data transfer is initiated with a START condition.

8.3.5 Stop Data Transfer

A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition

(P). Each data transfer is terminated with a STOP condition; however, if the master still wishes to communicate

on the bus, it can generate a repeated START condition and address another slave without first generating a

STOP condition.