C161O datasheet(40/66 Pages) INFINEON

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C161K

C161O

Data Sheet

V2.0, 2001-01

AC Characteristics

Definition of Internal Timing

The internal operation of the C161K/O is controlled by the internal CPU clock

fCPU. Both

edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)

operations.

The specification of the external timing (AC Characteristics) therefore depends on the

time between two consecutive edges of the CPU clock, called “TCL” (see Figure 8).

Figure 8

Generation Mechanisms for the CPU Clock

The CPU clock signal

fCPU can be generated from the oscillator clock signal fOSC via

different mechanisms. The duration of TCLs and their variation (and also the derived

external timing) depends on the used mechanism to generate

fCPU. This influence must

be regarded when calculating the timings for the C161K/O.

The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG

in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic

levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the

logic levels on pins P0.15-13 (P0H.7-5).

Table 9 associates the combinations of these three bits with the respective clock

generation mode.

MCT04826

OSC

CPU

Direct Clock Drive

OSC

CPU

Prescaler Operation

TCL

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