C161O datasheet(48/66 Pages) INFINEON

48 / 66 page

C161K

C161O

Data Sheet

V2.0, 2001-01

AC Characteristics

Multiplexed Bus (Reduced Supply Voltage Range)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2

tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

ALE high time

11 +

–

TCL - 14

–

Address setup to ALE

5 +

–

TCL - 20

–

Address hold after ALE

15 +

–

TCL - 10

–

ALE falling edge to RD,

WR (with RW-delay)

15 +

–

TCL - 10

–

ALE falling edge to RD,

WR (no RW-delay)

-10 +

tA –

-10 +

–

Address float after RD,

WR (with RW-delay)

t10 CC –

–

6ns

Address float after RD,

WR (no RW-delay)

t11 CC –

–

TCL + 6

RD, WR low time

(with RW-delay)

t12 CC 34 + tC

–

2TCL - 16

–

RD, WR low time

(no RW-delay)

t13 CC 59 + tC

–

3TCL - 16

–

RD to valid data in

(with RW-delay)

t14 SR –

22 +

–

2TCL - 28

RD to valid data in

(no RW-delay)

t15 SR –

47 +

–

3TCL - 28

ALE low to valid data in

t16 SR –

45 +

–

3TCL - 30

tA + tC

Address to valid data in

t17 SR –

57 + 2

–

4TCL - 43

+ 2

tA + tC

Data hold after RD

rising edge

t18 SR 0

–

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