C161O datasheet(49/66 Pages) INFINEON

49 / 66 page

C161K

C161O

Data Sheet

V2.0, 2001-01

Data float after RD

t19 SR –

36 +

–

2TCL - 14

Data valid to WR

t22 CC 24 + tC

–

2TCL - 26

–

Data hold after WR

t23 CC 36 + tF

–

2TCL - 14

–

ALE rising edge after RD,

t25 CC 36 + tF

–

2TCL - 14

–

Address hold after RD,

t27 CC 36 + tF

–

2TCL - 14

–

ALE falling edge to CS1)

t38 CC -8 - tA

10 -

-8 -

10 -

CS low to Valid Data In1)

t39 SR –

47+

+ 2

–

3TCL - 28

tC + 2tA

CS hold after RD, WR1)

t40 CC 57 + tF

–

3TCL - 18

–

ALE fall. edge to RdCS,

WrCS (with RW delay)

t42 CC 19 + tA

–

TCL - 6

–

ALE fall. edge to RdCS,

WrCS (no RW delay)

t43 CC -6 + tA

–

-6

–

Address float after RdCS,

WrCS (with RW delay)

t44 CC –

–

0ns

Address float after RdCS,

WrCS (no RW delay)

t45 CC –

–

TCL

RdCS to Valid Data In

(with RW delay)

t46 SR –

20 +

–

2TCL - 30

RdCS to Valid Data In

(no RW delay)

t47 SR –

45 +

–

3TCL - 30

RdCS, WrCS Low Time

(with RW delay)

t48 CC 38 + tC

–

2TCL - 12

–

RdCS, WrCS Low Time

(no RW delay)

t49 CC 63 + tC

–

3TCL - 12

–

Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2

tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

C161O Datasheet(PDF) 49 Page - Infineon Technologies AG

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