PEB2055 datasheet(79/269 Pages) INFINEON

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PEB 2055

PEF 2055

Detailed Register Description

Semiconductor Group

SIN

Synchronous transfer Interrupt; The SIN interrupt is enabled if at least one

synchronous transfer channel (A and/or B) is enabled via the STCR:TAE,

TBE bits. The SIN interrupt is generated when the access window for the

µP

opens. After the occurrence of the SIN interrupt the

µP can read and/or write

the synchronous transfer data registers (STDA, STDB). The SIN bit is reset

by reading ISTA.

SOV

Synchronous transfer Overflow; The SOV interrupt is generated if the

µP fails

to access the data registers (STDA, STDB) within the access window. The

SOV bit is reset by reading ISTA.

4.2.6.6 Mask Register (MASK)

Access in demultiplexed

µP-interface mode:

write

address: EH

OMDR:RBS = 0

Access in multiplexed

µP-interface mode:

write

address: 1CH

Reset value: 00H

A logical 1 disables the corresponding interrupt as described in the ISTA-register.

A masked interrupt is stored internally and reported in ISTA immediately if the mask is

released. However, an SFI interrupt is also reported in ISTA if masked. In this case no

interrupt is generated. When writing register MASK while ISTA indicates a non masked

interrupt INT is temporarily set into the inactive state.

bit 7

bit 0

TIN

SFI

MFFI

MAC

PFI

PIM

SIN

SOV

PEB2055 Datasheet(PDF) 79 Page - Infineon Technologies AG

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