PEB2055 datasheet(12/269 Pages) INFINEON

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PEB 2055

PEF 2055

Overview

Semiconductor Group

PDC

PCM Interface Data Clock

Single or double data rate.

RxD0

RxD1

RxD2

RxD3

Receive PCM Interface Data

Time-slot oriented data is received on this pins

and forwarded into the downstream data memory

of the EPIC.

TxD0

TxD1

TxD2

TxD3

Transmit PCM Interface Data

Time slot oriented data is shifted out of the

EPIC’s upstream data memory on this lines. For

time-slots which are flagged in the tristate

data memory or when bit OMDR:PSB is reset

the pins are set to high impedance state.

TSC0

TSC1

TSC2

TSC3

Tristate Control

Supplies a control signal for an external driver.

These lines are “low” when the corresponding

TxD outputs are valid. During reset these lines

are “high”.

FSC

I/O

Frame Synchronization

Input or output in IOM configuration. Direction

indication signal in SLD mode.

DCL

I/O

Data Clock

Input or output in IOM, slave clock in SLD

configuration. In IOM configuration single or

double data rate, single data rate in SLD mode.

36 *

35 *

DU0/SIP4

DU1/SIP5

DU2/SIP6

DU3/SIP7

I/IO (OD)

Data Upstream Input; IOM or PCM configuration.

Serial Interface Port, SLD configuration.

Depending on the bit OMDR:COS these lines

have push pull or open drain characteristic.

For unassigned channels or when bit

OMDR:CSB is reset the pins are in the state

high impedance.

* Note: EPIC-1 only

1.3

Pin Definitions and Functions (cont’d)

Pin No.

EPIC-S EPIC

Symbol Input (I)

Output (O)

Function

PEB2055 Datasheet(PDF) 12 Page - Infineon Technologies AG

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