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DRV8301

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SLOS719F – AUGUST 2011 – REVISED JANUARY 2016

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Copyright © 2011–2016, Texas Instruments Incorporated

7.5 Programming

7.5.1 SPI Communication

7.5.1.1 SPI

The DRV8301 SPI operates as a slave. The SPI input (SDI) data format consists of a 16 bit word with 1

read/write bit, 4 address bits, and 11 data bits. The SPI output (SDO) data format consists of a 16 bit word with 1

frame fault bit, 4 address bits, and 11 data bits. When a frame is not valid, frame fault bit will set to 1 and the

remaining bits will shift out as 0.

A valid frame must meet following conditions:

•

Clock must be low when nSCS goes low.

•

Should have 16 full clock cycles.

•

Clock must be low when nSCS goes high.

When nSCS is asserted high, any signals at the SCLK and SDI pins are ignored and SDO is forced into a high

impedance state. When nSCS transitions from HIGH to LOW, SDO is enabled and the SDO response word

loads into the shift register based on the previous SPI input word.

The SCLK pin must be low when nSCS transitions low. While nSCS is low, at each rising edge of the clock the

response word is serially shifted out on the SDO pin with the MSB shifted out first.

While SCS is low, at each falling edge of the clock the new input word is sampled on the SDI pin. The SPI input

word is decoded to determine the register address and access type (read or write). The MSB will be shifted in

first. Any amount of time may pass between bits, as long as nSCS stays active low. This allows two 8-bit words

to be used. If the input word sent to SDI is less than 16 bits or more than 16 bits, it is considered a frame error. If

it is a write command, the data will be ignored. The fault bit in the next SDO response word will then report 1.

After the 16th clock cycle or when nSCS transitions from LOW to HIGH, the SDI shift register data is transferred

into a latch where the input word is decoded.

For a READ command (Nth cycle) sent to SDI, SDO will respond with the data at the specified address in the

next cycle. (N+1)

For a WRITE command (Nth cycle) sent to SDI, SDO will respond with the data in Status Register 1 (0x00) in the

next cycle (N+1). This feature is intended to maximize SPI communication efficiency when having multiple write

commands.

7.5.1.2 SPI Format

The SDI input data word is 16 bits long and consists of:

•

1 read/write bit W [15]

•

4 address bits A [14:11]

•

11 data bits D [10:0]

The SDO output data word is 16 bits long and consists of:

•

1 fault frame bit F [15]

•

4 address bits A [14:11]

•

11 data bits D [10:0]

The SDO output word (Nth cycle) is in response to the previous SDI input word (N-1 cycle).

Therefore each SPI Query/Response pair requires two full 16 bit shift cycles to complete.

Table 6. SPI Input Data Control Word Format

R/W

ADDRESS

DATA

Word Bit

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Command

W0

A3

A2

A1

A0

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0