1

CP1

2

CP2

3

VCP

4

VMA

5

AOUT1

6

ISENA

7

AOUT2

8

BOUT2

9

ISENB

10

BOUT1

11

VMB

12

AVREF

13

BVREF

14

GND

28

GND

27

BI1

26

BI0

25

AI1

24

AI0

23

BIN2

22

BIN1

21

AIN1

20

AIN2

19

DECAY

18

nFAULT

17

nSLEEP

16

nRESET

15

V3P3OUT

GND

(PowerPAD)

DRV8843

www.ti.com

SLVSAS8D – APRIL 2011 – REVISED NOVEMBER 2015

5 Pin Configuration and Functions

PWP Package

28-Pin HTSSOP with PowerPAD™

Top View

Pin Functions

PIN

EXTERNAL COMPONENTS

DESCRIPTION

OR CONNECTIONS

NAME

PIN

POWER AND GROUND

GND

14, 28

-

Device ground

VMA

4

-

Bridge A power supply

Connect to motor supply (8.2 V to 45 V). Both pins must be

connected to the same supply, bypassed with a 0.1-uF

capacitor to GND, and connected to appropriate bulk

VMB

11

-

Bridge B power supply

capacitance.

Bypass to GND with a 0.47-

μF 6.3-V ceramic capacitor. Can

V3P3OUT

15

O

3.3-V regulator output

be used to supply VREF.

CP1

1

IO

Charge pump flying capacitor

Connect a 0.01-

μF 50-V capacitor between CP1 and CP2.

CP2

2

IO

Charge pump flying capacitor

Connect a 0.1-

μF 16-V ceramic capacitor and a 1-MΩ

VCP

3

IO

High-side gate drive voltage

resistor to VM.

CONTROL

AIN1

21

I

Bridge A input 1

Logic input controls state of AOUT1. Internal pulldown.

AIN2

20

I

Bridge A input 2

Logic input controls state of AOUT2. Internal pulldown.

AI0

24

I

Sets bridge A current: 00 = 100%,

Bridge A current set

01 = 71%, 10 = 38%, 11 = 0

AI1

25

I

Internal pulldown.

BIN1

22

I

Bridge B input 1

Logic input controls state of BOUT1. Internal pulldown.

BIN2

23

I

Bridge B input 2

Logic input controls state of BOUT2. Internal pulldown.

BI0

26

I

Sets bridge B current: 00 = 100%,

Bridge B current set

01 = 71%, 10 = 38%, 11 = 0

BI1

27

I

Internal pulldown.

Low = slow decay, open = mixed decay,

DECAY

19

I

Decay mode

high = fast decay

Internal pulldown and pullup.

Active-low reset input initializes internal logic and disables

nRESET

16

I

Reset input

the H-bridge outputs. Internal pulldown.

Logic high to enable device, logic low to enter low-power

nSLEEP

17

I

Sleep mode input

sleep mode. Internal pulldown.

AVREF

12

I

Bridge A current set reference input

Reference voltage for winding current set. Can be driven

individually with an external DAC for microstepping, or tied

BVREF

13

I

Bridge B current set reference input

to a reference (e.g., V3P3OUT).

STATUS

nFAULT

18

OD

Fault

Logic low when in fault condition (overtemp, overcurrent)

(1)

Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output

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